X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fnet%2Fsmc91111.c;h=ec4e8e928cb6edd387067608d000d83c0fb89f62;hb=b75d8dc5642b71eb029e7cd38031a32029e736cc;hp=6dc7ad52e4cb9d981d5c45e2b21df38aafa5fe77;hpb=9f09864003a74a1e3530eef42460eafa509ad210;p=platform%2Fkernel%2Fu-boot.git diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 6dc7ad5..ec4e8e9 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /*------------------------------------------------------------------------ . smc91111.c . This is a driver for SMSC's 91C111 single-chip Ethernet device. @@ -10,19 +11,6 @@ . Developed by Simple Network Magic Corporation (SNMC) . Copyright (C) 1996 by Erik Stahlman (ES) . - . This program is free software; you can redistribute it and/or modify - . it under the terms of the GNU General Public License as published by - . the Free Software Foundation; either version 2 of the License, or - . (at your option) any later version. - . - . This program is distributed in the hope that it will be useful, - . but WITHOUT ANY WARRANTY; without even the implied warranty of - . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - . GNU General Public License for more details. - . - . You should have received a copy of the GNU General Public License - . along with this program; if not, write to the Free Software - . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA . . Information contained in this file was obtained from the LAN91C111 . manual from SMC. To get a copy, if you really want one, you can find @@ -63,6 +51,7 @@ #include #include #include +#include #include "smc91111.h" #include @@ -178,8 +167,6 @@ static void smc_phy_configure(struct eth_device *dev); * inx,outx functions fixed this problem. */ -#define barrier() __asm__ __volatile__("": : :"memory") - static inline word SMC_inw(struct eth_device *dev, dword offset) { word v; @@ -280,7 +267,7 @@ static inline void smc_wait_mmu_release_complete (struct eth_device *dev) /* assume bank 2 selected */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (1); /* Wait until not busy */ + udelay(1); /* Wait until not busy */ if (++count > 200) break; } @@ -332,7 +319,7 @@ static void smc_reset (struct eth_device *dev) SMC_SELECT_BANK (dev, 0); /* this should pause enough for the chip to be happy */ - udelay (10); + udelay(10); /* Disable transmit and receive functionality */ SMC_outw (dev, RCR_CLEAR, RCR_REG); @@ -347,7 +334,7 @@ static void smc_reset (struct eth_device *dev) smc_wait_mmu_release_complete (dev); SMC_outw (dev, MC_RESET, MMU_CMD_REG); while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) - udelay (1); /* Wait until not busy */ + udelay(1); /* Wait until not busy */ /* Note: It doesn't seem that waiting for the MMU busy is needed here, but this is a place where future chipsets _COULD_ break. Be wary @@ -513,15 +500,8 @@ again: } /* we have a packet address, so tell the card to use it */ -#ifndef CONFIG_XAENIAX SMC_outb (dev, packet_no, PN_REG); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl (dev, packet_no << 16, 0); -#endif + /* do not write new ptr value if Write data fifo not empty */ while ( saved_ptr & PTR_NOTEMPTY ) printf ("Write data fifo not empty!\n"); @@ -556,39 +536,19 @@ again: */ #ifdef USE_32_BIT SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); -#ifndef CONFIG_XAENIAX if (length & 0x2) SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); #else - /* On XANEIAX, we can only use 32-bit writes, so we need to handle - * unaligned tail part specially. The standard code doesn't work. - */ - if ((length & 3) == 3) { - u16 * ptr = (u16*) &buf[length-3]; - SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), - SMC91111_DATA_REG); - } else if ((length & 2) == 2) { - u16 * ptr = (u16*) &buf[length-2]; - SMC_outl(dev, *ptr, SMC91111_DATA_REG); - } else if (length & 1) { - SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); - } else { - SMC_outl(dev, 0, SMC91111_DATA_REG); - } -#endif -#else SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ -#ifndef CONFIG_XAENIAX /* Send the last byte, if there is one. */ if ((length & 1) == 0) { SMC_outw (dev, 0, SMC91111_DATA_REG); } else { SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); } -#endif /* and let the chipset deal with it */ SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); @@ -602,13 +562,10 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (10); + udelay(10); } PRINTK2 ("MMU ready\n"); @@ -624,13 +581,10 @@ again: /* release packet */ /* no need to release, MMU does that now */ -#ifdef CONFIG_XAENIAX - SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); -#endif /* wait for MMU getting ready (low) */ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { - udelay (10); + udelay(10); } PRINTK2 ("MMU ready\n"); @@ -639,15 +593,7 @@ again: } /* restore previously saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl(dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); return length; @@ -681,7 +627,7 @@ static int smc_write_hwaddr(struct eth_device *dev) * Set up everything, reset the card, etc .. * */ -static int smc_init(struct eth_device *dev, bd_t *bd) +static int smc_init(struct eth_device *dev, struct bd_info *bd) { swap_to(ETHERNET); @@ -770,35 +716,35 @@ static int smc_rcv(struct eth_device *dev) #ifdef USE_32_BIT - PRINTK3(" Reading %d dwords (and %d bytes) \n", + PRINTK3(" Reading %d dwords (and %d bytes)\n", packet_length >> 2, packet_length & 3 ); /* QUESTION: Like in the TX routine, do I want to send the DWORDs or the bytes first, or some mixture. A mixture might improve already slow PIO performance */ - SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], - packet_length >> 2 ); + SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0], + packet_length >> 2); /* read the left over bytes */ if (packet_length & 3) { int i; - byte *tail = (byte *)(NetRxPackets[0] + + byte *tail = (byte *)(net_rx_packets[0] + (packet_length & ~3)); dword leftover = SMC_inl(dev, SMC91111_DATA_REG); for (i=0; i<(packet_length & 3); i++) *tail++ = (byte) (leftover >> (8*i)) & 0xff; } #else - PRINTK3(" Reading %d words and %d byte(s) \n", + PRINTK3(" Reading %d words and %d byte(s)\n", (packet_length >> 1 ), packet_length & 1 ); - SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], - packet_length >> 1); + SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0], + packet_length >> 1); #endif /* USE_32_BIT */ #if SMC_DEBUG > 2 printf("Receiving Packet\n"); - print_packet( NetRxPackets[0], packet_length ); + print_packet(net_rx_packets[0], packet_length); #endif } else { /* error ... */ @@ -816,20 +762,12 @@ static int smc_rcv(struct eth_device *dev) udelay(1); /* Wait until not busy */ /* restore saved registers */ -#ifndef CONFIG_XAENIAX SMC_outb( dev, saved_pnr, PN_REG ); -#else - /* On Xaeniax board, we can't use SMC_outb here because that way - * the Allocate MMU command will end up written to the command register - * as well, which will lead to a problem. - */ - SMC_outl( dev, saved_pnr << 16, 0); -#endif SMC_outw( dev, saved_ptr, PTR_REG ); if (!is_error) { /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[0], packet_length); + net_process_received_packet(net_rx_packets[0], packet_length); return packet_length; } else { return 0; @@ -1020,19 +958,19 @@ static word smc_read_phy_register (struct eth_device *dev, byte phyreg) for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ SMC_outw (dev, mii_reg, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ SMC_SELECT_BANK (dev, oldBank); @@ -1141,19 +1079,19 @@ static void smc_write_phy_register (struct eth_device *dev, byte phyreg, for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ SMC_outw (dev, mii_reg | bits[i], MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ SMC_outw (dev, mii_reg, MII_REG); - udelay (SMC_PHY_CLOCK_DELAY); + udelay(SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ SMC_SELECT_BANK (dev, oldBank);