X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fnet%2Ffm%2Fmemac_phy.c;h=5f910c2cdd3025086aba99a15e14118134d7de69;hb=1899fac925eda817e12234aef3d01d354788662e;hp=140e59b75c45696b56c14d16b603afbc98178539;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 140e59b..5f910c2 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
- *	Andy Fleming <afleming@freescale.com>
+ *	Andy Fleming <afleming@gmail.com>
  *	Roy Zang <tie-fei.zang@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-	} else {
+	} else
 		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-	}
 
 	/* Wait till the bus is free */
 	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
@@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-	} else {
+	} else
 		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-	}
 
 	/* Wait till the bus is free */
 	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
@@ -133,5 +129,17 @@ int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
 
 	bus->priv = info->regs;
 
+	/*
+	 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
+	 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
+	 * (much higher than 2.5MHz), violating the IEEE specs.
+	 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
+	 * is zero, so MDIO clock is disabled.
+	 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
+	 * be properly initialized.
+	 */
+	setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
+		     MDIO_STAT_CLKDIV(258));
+
 	return mdio_register(bus);
 }