X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fmmc%2Fzynq_sdhci.c;h=28cedf0c468b3027c4ac6394f2fcb76f0f5159f5;hb=61e745d1311532a90de537cc470da12d306ee193;hp=9e37af45fc658eca8a836b63d2aaa0b92c9cbea8;hpb=f0df254663d44f7fd4b714542bb4602626837465;p=platform%2Fkernel%2Fu-boot.git diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 9e37af4..28cedf0 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -1,40 +1,114 @@ /* - * (C) Copyright 2013 Inc. + * (C) Copyright 2013 - 2015 Xilinx, Inc. * * Xilinx Zynq SD Host Controller Interface * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 Temple - * Place, Suite 330, Boston, MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ +#include #include +#include +#include +#include #include #include -#include -int zynq_sdhci_init(u32 regbase) +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ +# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 +#endif + +struct arasan_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; + unsigned int f_max; +}; + +static int arasan_sdhci_probe(struct udevice *dev) { - struct sdhci_host *host = NULL; + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_host *host = dev_get_priv(dev); + struct clk clk; + unsigned long clock; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } - host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); - if (!host) { - printf("zynq_sdhci_init: sdhci_host malloc fail\n"); - return 1; + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | + SDHCI_QUIRK_BROKEN_R1B; + +#ifdef CONFIG_ZYNQ_HISPD_BROKEN + host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; +#endif + + host->max_clk = clock; - host->name = "zynq_sdhci"; - host->ioaddr = (void *)regbase; - host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD; - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, + CONFIG_ZYNQ_SDHCI_MIN_FREQ); + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; - host->host_caps = MMC_MODE_HC; + return sdhci_probe(dev); +} + +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + + plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ); - add_sdhci(host, 52000000, 52000000 >> 9); return 0; } + +static int arasan_sdhci_bind(struct udevice *dev) +{ + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-8.9a" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = arasan_sdhci_bind, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), +};