X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Finca-ip_sw.c;h=e4aaed6afbc6c1709987c5fbc3226cc0a5487525;hb=d61ea14885631e58a25feaa81ee82eb464c62d6a;hp=42edca880f7fb8094a8ca7ef2b91b0cad52339d7;hpb=cf56e1101957c09cb4aafcf28a89658c4649c511;p=platform%2Fkernel%2Fu-boot.git diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index 42edca8..e4aaed6 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -1,7 +1,7 @@ /* * INCA-IP internal switch ethernet driver. * - * (C) Copyright 2003 + * (C) Copyright 2003-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -14,7 +14,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -26,8 +26,8 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_INCA_IP_SWITCH) +#if defined(CONFIG_CMD_NET) \ + && defined(CONFIG_NET_MULTI) && defined(CONFIG_INCA_IP_SWITCH) #include #include @@ -41,53 +41,66 @@ #define DELAY udelay(10000) + /* Sometimes the store word instruction hangs while writing to one + * of the Switch registers. Moving the instruction into a separate + * function somehow makes the problem go away. + */ +static void SWORD(volatile u32 * reg, u32 value) +{ + *reg = value; +} #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) #define SW_WRITE_REG(reg, value) \ - *((volatile u32*)reg) = (u32)value;\ - DELAY;\ - *((volatile u32*)reg) = (u32)value; + SWORD(reg, value);\ + DELAY;\ + SWORD(reg, value); -#define SW_READ_REG(reg, value) \ - value = (u32)*((volatile u32*)reg);\ - DELAY;\ - value = (u32)*((volatile u32*)reg); +#define SW_READ_REG(reg, value) \ + value = (u32)*((volatile u32*)reg);\ + DELAY;\ + value = (u32)*((volatile u32*)reg); -#define INCA_DMA_TX_POLLING_TIME 0x07 -#define INCA_DMA_RX_POLLING_TIME 0x07 +#define INCA_DMA_TX_POLLING_TIME 0x07 +#define INCA_DMA_RX_POLLING_TIME 0x07 -#define INCA_DMA_TX_HOLD 0x80000000 -#define INCA_DMA_TX_EOP 0x40000000 -#define INCA_DMA_TX_SOP 0x20000000 -#define INCA_DMA_TX_ICPT 0x10000000 -#define INCA_DMA_TX_IEOP 0x08000000 +#define INCA_DMA_TX_HOLD 0x80000000 +#define INCA_DMA_TX_EOP 0x40000000 +#define INCA_DMA_TX_SOP 0x20000000 +#define INCA_DMA_TX_ICPT 0x10000000 +#define INCA_DMA_TX_IEOP 0x08000000 -#define INCA_DMA_RX_C 0x80000000 -#define INCA_DMA_RX_SOP 0x40000000 -#define INCA_DMA_RX_EOP 0x20000000 +#define INCA_DMA_RX_C 0x80000000 +#define INCA_DMA_RX_SOP 0x40000000 +#define INCA_DMA_RX_EOP 0x20000000 + +#define INCA_SWITCH_PHY_SPEED_10H 0x1 +#define INCA_SWITCH_PHY_SPEED_10F 0x5 +#define INCA_SWITCH_PHY_SPEED_100H 0x2 +#define INCA_SWITCH_PHY_SPEED_100F 0x6 /************************ Auto MDIX settings ************************/ -#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR -#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL -#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT -#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 - -#define WAIT_SIGNAL_RETRIES 100 -#define WAIT_LINK_RETRIES 100 -#define LINK_RETRY_DELAY 300 /* ms */ +#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR +#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL +#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT +#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 + +#define WAIT_SIGNAL_RETRIES 100 +#define WAIT_LINK_RETRIES 100 +#define LINK_RETRY_DELAY 2000 /* ms */ /********************************************************************/ typedef struct { union { struct { - volatile u32 HOLD :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 offset :3; - volatile u32 reserved0 :4; - volatile u32 NFB :22; + volatile u32 HOLD :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 offset :3; + volatile u32 reserved0 :4; + volatile u32 NFB :22; }field; volatile u32 word; @@ -99,11 +112,11 @@ typedef struct union { struct { - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved3 :12; - volatile u32 NBT :17; + volatile u32 C :1; + volatile u32 Sop :1; + volatile u32 Eop :1; + volatile u32 reserved3 :12; + volatile u32 NBT :17; }field; volatile u32 word; @@ -116,13 +129,13 @@ typedef struct { union { struct { - volatile u32 HOLD :1; - volatile u32 Eop :1; - volatile u32 Sop :1; - volatile u32 ICpt :1; - volatile u32 IEop :1; - volatile u32 reserved0 :5; - volatile u32 NBA :22; + volatile u32 HOLD :1; + volatile u32 Eop :1; + volatile u32 Sop :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 reserved0 :5; + volatile u32 NBA :22; }field; volatile u32 word; @@ -132,8 +145,8 @@ typedef struct volatile u32 TxDataPtr; - volatile u32 C :1; - volatile u32 reserved3 :31; + volatile u32 C :1; + volatile u32 reserved3 :31; } inca_tx_descriptor_t; @@ -143,12 +156,11 @@ static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); static int tx_new, rx_new, tx_hold, rx_hold; static int tx_old_hold = -1; -static int initialized = 0; +static int initialized = 0; static int inca_switch_init(struct eth_device *dev, bd_t * bis); -static int inca_switch_send(struct eth_device *dev, volatile void *packet, - int length); +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length); static int inca_switch_recv(struct eth_device *dev); static void inca_switch_halt(struct eth_device *dev); static void inca_init_switch_chip(void); @@ -173,8 +185,10 @@ int inca_switch_initialize(bd_t * bis) inca_dma_init(); inca_init_switch_chip(); - + +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) inca_amdix(); +#endif sprintf(dev->name, "INCA-IP Switch"); dev->init = inca_switch_init; @@ -219,8 +233,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Initialize the descriptor rings. */ - for (i = 0; i < NUM_RX_DESC; i++) - { + for (i = 0; i < NUM_RX_DESC; i++) { inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]); memset(rx_desc, 0, sizeof(rx_ring[i])); @@ -259,9 +272,9 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) memset(tx_desc, 0, sizeof(tx_ring[i])); - tx_desc->params.word = 0; + tx_desc->params.word = 0; tx_desc->params.field.HOLD = 1; - tx_desc->C = 1; + tx_desc->C = 1; /* Check if it is the last descriptor. */ @@ -290,8 +303,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Writing to the COMMAND REG. */ - DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, - INCA_IP_DMA_DMA_RXCCR0_INIT); + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); /* Initialize TxDMA. */ @@ -314,9 +326,9 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) #endif /* enable spanning tree forwarding, enable the CPU port */ /* ST_PT: - * CPS (CPU port status) 0x3 (forwarding) - * LPS (LAN port status) 0x3 (forwarding) - * PPS (PC port status) 0x3 (forwarding) + * CPS (CPU port status) 0x3 (forwarding) + * LPS (LAN port status) 0x3 (forwarding) + * PPS (PC port status) 0x3 (forwarding) */ SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); @@ -328,14 +340,13 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) } -static int inca_switch_send(struct eth_device *dev, volatile void *packet, - int length) +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length) { - int i; - int res = -1; - u32 command; - u32 regValue; - inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); + int i; + int res = -1; + u32 command; + u32 regValue; + inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); #if 0 printf("Entered inca_switch_send()\n"); @@ -368,7 +379,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0; tx_hold = tx_new; - tx_new = (tx_new + 1) % NUM_TX_DESC; + tx_new = (tx_new + 1) % NUM_TX_DESC; if (! initialized) { @@ -404,7 +415,7 @@ Done: static int inca_switch_recv(struct eth_device *dev) { - int length = 0; + int length = 0; inca_rx_descriptor_t * rx_desc; #if 0 @@ -445,8 +456,7 @@ static int inca_switch_recv(struct eth_device *dev) #if 0 printf("Received %d bytes\n", length); #endif - NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), - length - 4); + NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4); } else { #if 1 printf("Zero length!!!\n"); @@ -511,13 +521,13 @@ static void inca_init_switch_chip(void) #if 1 /* init MDIO configuration: - * MDS (Poll speed): 0x01 (4ms) - * PHY_LAN_ADDR: 0x06 - * PHY_PC_ADDR: 0x05 + * MDS (Poll speed): 0x01 (4ms) + * PHY_LAN_ADDR: 0x06 + * PHY_PC_ADDR: 0x05 * UEP (Use External PHY): 0x00 (Internal PHY is used) - * PS (Port Select): 0x00 (PT/UMM for LAN) - * PT (PHY Test): 0x00 (no test mode) - * UMM (Use MDIO Mode): 0x00 (state machine is disabled) + * PS (Port Select): 0x00 (PT/UMM for LAN) + * PT (PHY Test): 0x00 (no test mode) + * UMM (Use MDIO Mode): 0x00 (state machine is disabled) */ SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); @@ -535,39 +545,39 @@ static void inca_init_switch_chip(void) /* MDIO_ACC: * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x05 (PC) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x05 (PC) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal + * PD (power down) - normal + * ISO (isolate) - normal * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex + * DM (duplex mode) - half duplex * CT (collision test) - enable */ SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); /* MDIO_ACC: * RA (Request/Ack) 0x01 (Request) - * RW (Read/Write) 0x01 (Write) - * PHY_ADDR 0x06 (LAN) - * REG_ADDR 0x00 (PHY_BCR: basic control register) - * PHY_DATA 0x8000 - * Reset - software reset - * LB (loop back) - normal - * SS (speed select) - 10 Mbit/s + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x06 (LAN) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s * ANE (auto neg. enable) - enable - * PD (power down) - normal - * ISO (isolate) - normal + * PD (power down) - normal + * ISO (isolate) - normal * RAN (restart auto neg.) - normal - * DM (duplex mode) - half duplex + * DM (duplex mode) - half duplex * CT (collision test) - enable */ - SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); #endif @@ -623,9 +633,15 @@ static void inca_dma_init(void) DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); } +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) static int inca_amdix(void) { - u32 regValue = 0; + u32 phyReg1 = 0; + u32 phyReg4 = 0; + u32 phyReg5 = 0; + u32 phyReg6 = 0; + u32 phyReg31 = 0; + u32 regEphy = 0; int mdi_flag; int retries; @@ -634,31 +650,29 @@ static int inca_amdix(void) *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); +#if 0 /* Wait for signal. */ retries = WAIT_SIGNAL_RETRIES; - while (--retries) - { + while (--retries) { SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ (17 << 16)); /* PHY_MCSR */ - do - { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue); - } - while (regValue & (1 << 31)); + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); - if (regValue & (1 << 1)) - { + if (phyReg1 & (1 << 1)) { /* Signal detected */ break; } } if (!retries) - return -1; + goto Fail; +#endif /* Set MDI mode. */ @@ -668,43 +682,136 @@ static int inca_amdix(void) /* Wait for link. */ retries = WAIT_LINK_RETRIES; - while (--retries) - { + while (--retries) { udelay(LINK_RETRY_DELAY * 1000); SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, (0x1 << 31) | /* RA */ (0x0 << 30) | /* Read */ (0x6 << 21) | /* LAN */ (1 << 16)); /* PHY_BSR */ - do - { - SW_READ_REG(INCA_IP_Switch_MDIO_ACC, regValue); - } - while (regValue & (1 << 31)); + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); - if (regValue & (1 << 2)) - { + if (phyReg1 & (1 << 2)) { /* Link is up */ break; - } - else if (mdi_flag) - { + } else if (mdi_flag) { /* Set MDIX mode */ *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); mdi_flag = 0; - } - else - { + } else { /* Set MDI mode */ *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); mdi_flag = 1; } } - if (!retries) - return -1; + if (!retries) { + goto Fail; + } else { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (1 << 16)); /* PHY_BSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + /* Auto-negotiation / Parallel detection complete + */ + if (phyReg1 & (1 << 5)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (31 << 16)); /* PHY_SCSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); + } while (phyReg31 & (1 << 31)); + + switch ((phyReg31 >> 2) & 0x7) { + case INCA_SWITCH_PHY_SPEED_10H: + /* 10Base-T Half-duplex */ + regEphy = 0; + break; + case INCA_SWITCH_PHY_SPEED_10F: + /* 10Base-T Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_DL; + break; + case INCA_SWITCH_PHY_SPEED_100H: + /* 100Base-TX Half-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL; + break; + case INCA_SWITCH_PHY_SPEED_100F: + /* 100Base-TX Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; + break; + } + + /* In case of Auto-negotiation, + * update the negotiated PAUSE support status + */ + if (phyReg1 & (1 << 3)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (6 << 16)); /* PHY_ANER */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); + } while (phyReg6 & (1 << 31)); + + /* We are Autoneg-able. + * Is Link partner also able to autoneg? + */ + if (phyReg6 & (1 << 0)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (4 << 16)); /* PHY_ANAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); + } while (phyReg4 & (1 << 31)); + + /* We advertise PAUSE capab. + * Does link partner also advertise it? + */ + if (phyReg4 & (1 << 10)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (5 << 16)); /* PHY_ANLPAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); + } while (phyReg5 & (1 << 31)); + + /* Link partner is PAUSE capab. + */ + if (phyReg5 & (1 << 10)) { + regEphy |= INCA_IP_Switch_EPHY_PL; + } + } + } + + } + + /* Link is up */ + regEphy |= INCA_IP_Switch_EPHY_LL; + + SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); + } + } return 0; + +Fail: + printf("No Link on LAN port\n"); + return -1; } +#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ #endif