X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fddr%2Ffsl%2Futil.c;h=0a305b36b8b1a71ad0f9853bb1b4aab3b51d4586;hb=235c5b8315c6a9eb566fd3d99a098cc6db869fc5;hp=ce55aea1b48e51084e8499c356cc4eb457a23a20;hpb=86e6f7eaa15f0aca03bb7c961902563348c2dd05;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ce55aea..0a305b3 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,9 +1,7 @@
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #include <common.h>
@@ -15,6 +13,10 @@
 #include <fsl_ddr.h>
 #include <fsl_immap.h>
 #include <asm/io.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+	defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
 
 /* To avoid 64-bit full-divides, we factor this here */
 #define ULL_2E12 2000000000000ULL
@@ -32,17 +34,17 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
 	case 0:
 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 		break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 	case 1:
 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 		break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
 	case 2:
 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 		break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
 	case 3:
 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 		break;
@@ -176,23 +178,23 @@ void print_ddr_info(unsigned int start_ctrl)
 	struct ccsr_ddr __iomem *ddr =
 		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 
-#if	defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if	defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 #endif
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 	uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 #endif
 	uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 	int cas_lat;
 
-#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
 	if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 	    (start_ctrl == 1)) {
 		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 		sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 	}
 #endif
-#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
 	if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 	    (start_ctrl == 2)) {
 		ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
@@ -248,7 +250,7 @@ void print_ddr_info(unsigned int start_ctrl)
 	else
 		puts(", ECC off)");
 
-#if (CONFIG_NUM_DDR_CONTROLLERS == 3)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 #ifdef CONFIG_E6500
 	if (*mcintl3r & 0x80000000) {
 		puts("\n");
@@ -270,7 +272,7 @@ void print_ddr_info(unsigned int start_ctrl)
 	}
 #endif
 #endif
-#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 	if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
 		puts("\n");
 		puts("       DDR Controller Interleaving Mode: ");
@@ -339,8 +341,8 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 {
 	unsigned int i;
 	u32 ddrc_debug20;
-	u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
-	u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+	u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
+	u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
 	struct ccsr_ddr __iomem *ddr;
 
 	for (i = first_ctrl; i <= last_ctrl; i++) {
@@ -348,17 +350,17 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 		case 0:
 			ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 			break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 		case 1:
 			ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 			break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
 		case 2:
 			ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 			break;
 #endif
-#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
 		case 3:
 			ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 			break;
@@ -385,3 +387,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 		ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 }
 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
+
+void remove_unused_controllers(fsl_ddr_info_t *info)
+{
+#ifdef CONFIG_FSL_LSCH3
+	int i;
+	u64 nodeid;
+	void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
+	bool ddr0_used = false;
+	bool ddr1_used = false;
+
+	for (i = 0; i < 8; i++) {
+		nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
+		if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
+			ddr0_used = true;
+		} else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
+			ddr1_used = true;
+		} else {
+			printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
+			       nodeid);
+		}
+		hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
+	}
+	if (!ddr0_used && !ddr1_used) {
+		printf("Invalid configuration in HN-F SAM control\n");
+		return;
+	}
+
+	if (!ddr0_used && info->first_ctrl == 0) {
+		info->first_ctrl = 1;
+		info->num_ctrls = 1;
+		debug("First DDR controller disabled\n");
+		return;
+	}
+
+	if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
+		info->num_ctrls = 1;
+		debug("Second DDR controller disabled\n");
+	}
+#endif
+}