X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fclk%2Fclk_versal.c;h=075a08380d844cd69eafa30355b3e4997d95282f;hb=b641dd3ec8dc3f6b18d2fa945ac3ab597063d191;hp=e0fa661be9e081e2b73b92322e2e33bb4033868b;hpb=0f3604a2b3882bc0f6c66cfd5acbd074703a5814;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index e0fa661..075a083 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/bitfield.h>
 #include <malloc.h>
@@ -13,6 +14,7 @@
 #include <dm.h>
 #include <asm/arch/sys_proto.h>
 #include <zynqmp_firmware.h>
+#include <linux/err.h>
 
 #define MAX_PARENT			100
 #define MAX_NODES			6
@@ -363,7 +365,7 @@ static u32 versal_clock_get_div(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	u32 div;
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	div = ret_payload[1];
 
 	return div;
@@ -373,7 +375,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
 {
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
 
 	return div;
 }
@@ -383,7 +385,7 @@ static u64 versal_clock_ref(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	int ref;
 
-	versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
 	ref = ret_payload[0];
 	if (!(ref & 1))
 		return ref_clk;
@@ -402,7 +404,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
 	u32 parent_rate, parent_id;
 	u32 id = clk_id & 0xFFF;
 
-	versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
 	res = ret_payload[1];
 	if (!res) {
 		printf("0%x PLL not enabled\n", clk_id);
@@ -412,9 +414,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
 	parent_id = clock[clock[id].parent[0].id].clk_id;
 	parent_rate = versal_clock_ref(parent_id);
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	fbdiv = ret_payload[1];
-	versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
 	frac = ret_payload[1];
 
 	freq = (fbdiv * parent_rate) >> (1 << frac);
@@ -441,7 +443,7 @@ static u32 versal_clock_get_parentid(u32 clk_id)
 	u32 id = clk_id & 0xFFF;
 
 	if (versal_clock_mux(clk_id)) {
-		versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+		xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
 				  ret_payload);
 		parent_id = ret_payload[1];
 	}
@@ -501,6 +503,9 @@ static u64 versal_clock_calc(u32 clk_id)
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
 		return versal_clock_ref(clk_id);
 
+	if (!parent_id)
+		return 0;
+
 	clk_rate = versal_clock_calc(parent_id);
 
 	if (versal_clock_div(clk_id)) {
@@ -524,7 +529,7 @@ static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
 	     NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
 	    ((clk_id >> NODE_CLASS_SHIFT) &
 	     NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
-		if (!versal_clock_gate(clk_id))
+		if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
 			return -EINVAL;
 		*clk_rate = versal_clock_calc(clk_id);
 		return 0;
@@ -569,6 +574,12 @@ static void versal_get_clock_info(void)
 			continue;
 
 		clock[i].valid = attr & CLK_VALID_MASK;
+
+		/* skip query for Invalid clock */
+		ret = versal_is_valid_clock(i);
+		if (ret != CLK_VALID_MASK)
+			continue;
+
 		clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
 				CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
 		nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;