X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=doc%2FREADME.ppc440;h=dd8ccaad0e7ae32ef25636faa4403c44143047c0;hb=HEAD;hp=08f34f589faf08b63934c5463433c2bea2246791;hpb=038ccac511214b062c56f22b9413f784b86bcd87;p=kernel%2Fu-boot.git

diff --git a/doc/README.ppc440 b/doc/README.ppc440
index 08f34f5..dd8ccaa 100644
--- a/doc/README.ppc440
+++ b/doc/README.ppc440
@@ -47,25 +47,25 @@ the cpu-specific code (vs. board-specific code), so you should
 at least review these before deciding to make any changes ... it
 will probably save you some headaches ;-)
 
-CFG_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
+CONFIG_SYS_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0)
 
-CFG_FLASH_BASE - The virtual address where FLASH is mapped.
+CONFIG_SYS_FLASH_BASE - The virtual address where FLASH is mapped.
 
-CFG_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
+CONFIG_SYS_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped.
     This mapping provides access to PCI-bus memory.
 
-CFG_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
+CONFIG_SYS_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped
     peripherals are mapped. (e.g. -- UART registers, IIC registers, etc).
 
-CFG_ISRAM_BASE - The virtual address where the 440 internal SRAM is
+CONFIG_SYS_ISRAM_BASE - The virtual address where the 440 internal SRAM is
     mapped. The internal SRAM is equivalent to 405gp OCM and is used
     for the initial stack.
 
-CFG_PCI_BASE - The virtual address where the 440 PCI-x bridge config
+CONFIG_SYS_PCI_BASE - The virtual address where the 440 PCI-x bridge config
     registers are mapped.
 
-CFG_PCI_TARGBASE - The PCI address that is mapped to the virtual address
-    defined by CFG_PCI_MEMBASE.
+CONFIG_SYS_PCI_TARGBASE - The PCI address that is mapped to the virtual address
+    defined by CONFIG_SYS_PCI_MEMBASE.
 
 
 UART / SERIAL
@@ -73,41 +73,35 @@ UART / SERIAL
 
 The UART port works fine when an external serial clock is provided
 (like the one on the Ebony board) and when using internal clocking.
-This is controlled with the CFG_EXT_SERIAL_CLOCK flag. When using
+This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using
 internal clocking, the "ideal baud rate" settings in the 440GP
 user manual are automatically calculated.
 
-CONFIG_SERIAL_SOFTWARE_FIFO enables interrupt-driven serial operation.
-But the last time I checked, interrupts were initialized after the
-serial port causing the interrupt handler to be removed from the
-handler table. This will probably be fixed soon ... or fix it
-yourself and submit a patch :-)
-
 
 I2C
 =================
 
 The i2c utilities have been tested on both Rev B. and Rev C. and
-look good. The iprobe command implementation has been updated to
+look good. The 'i2c probe' command implementation has been updated to
 allow for 'skipped' addresses. Some i2c slaves are write only and
 cause problems when a probe (read) is performed (for example the
 CDCV850 clock controller at address 0x69 on the ebony board).
 
 To prevent probing certain addresses you can define the
-CFG_I2C_NOPROBES macro in your board-specific header file. When
+CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When
 defined, all specified addresses are skipped during a probe.
 The addresses that are skipped will be displayed in the output
-of the iprobe command.
+of the 'i2c probe' command.
 
 For example, to prevent probing address 0x69, define the macro as
 follows:
 
-#define CFG_I2C_NOPROBES {0x69}
+#define CONFIG_SYS_I2C_NOPROBES {0x69}
 
 Similarly, to prevent probing addresses 0x69 and 0x70, define the
 macro a:
 
-#define CFG_I2C_NOPROBES {0x69, 0x70}
+#define CONFIG_SYS_I2C_NOPROBES {0x69, 0x70}
 
 
 DDR SDRAM CONTROLLER
@@ -144,19 +138,20 @@ utilities once you get to the U-Boot command prompt. NOTE: the default
 The cpu-specific code sets up a default pci_controller structure
 that maps in a single PCI I/O space and PCI memory space. The I/O
 space begins at PCI I/O address 0 and the PCI memory space is
-256 MB starting at PCI address CFG_PCI_TARGBASE. After the
+256 MB starting at PCI address CONFIG_SYS_PCI_TARGBASE. After the
 pci_controller structure is initialized, the cpu-specific code will
-call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
-defined. This routine is implemented by board-specific code & is where
-the board can over-ride/extend the default pci_controller structure
-settings and do other pre-initialization tasks. If pci_pre_init()
-returns a value of zero, PCI initialization is aborted; otherwise the
-controller structure is registered and initialization continues.
+call the routine pci_pre_init(). This routine is implemented by
+board-specific code & is where the board can over-ride/extend the
+default pci_controller structure settings and exspecially provide
+a routine to map the PCI interrupts and do other pre-initialization
+tasks. If pci_pre_init() returns a value of zero, PCI initialization
+is aborted; otherwise the controller structure is registered and
+initialization continues.
 
 The default 440GP PCI target configuration is minimal -- it assumes that
 the strapping registers are set as necessary. Since the strapping bits
 provide very limited flexibility, you may want to customize the boards
-target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific
+target configuration. If CONFIG_SYS_PCI_TARGET_INIT is defined, the cpu-specific
 code will call the routine pci_target_init() which you must implement
 in your board-specific code.
 
@@ -165,7 +160,7 @@ initializing the subsystem id and subsystem vendor id, and then ensuring
 that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set.
 
 The default PCI master initialization maps in 256 MB of pci memory
-starting at PCI address CFG_PCI_MEMBASE. To customize this, define
+starting at PCI address CONFIG_SYS_PCI_MEMBASE. To customize this, define
 PCI_MASTER_INIT. This will call the routine pci_master_init() in your
 board-specific code rather than performing the default master
 initialization.