X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=doc%2FREADME.fsl-ddr;h=1243a1222760a8293b963fb5aca6a60ddcecb0b0;hb=HEAD;hp=abfb7f192de3e450dd000a501bf818f170e3375a;hpb=4e57382faa4bcad285baee21737de2c99ba6baad;p=kernel%2Fu-boot.git diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index abfb7f1..1243a12 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -1,5 +1,28 @@ - -Table of interleaving modes supported in cpu/8xxx/ddr/ +Table of interleaving 2-4 controllers +===================================== + +--------------+-----------------------------------------------------------+ + |Configuration | Memory Controller | + | | 1 2 3 4 | + |--------------+--------------+--------------+-----------------------------+ + | Two memory | Not Intlv'ed | Not Intlv'ed | | + | complexes +--------------+--------------+ | + | | 2-way Intlv'ed | | + |--------------+--------------+--------------+--------------+ | + | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | | + | Three memory +--------------+--------------+--------------+ | + | complexes | 2-way Intlv'ed | Not Intlv'ed | | + | +-----------------------------+--------------+ | + | | 3-way Intlv'ed | | + +--------------+--------------+--------------+--------------+--------------+ + | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | + | Four memory +--------------+--------------+--------------+--------------+ + | complexes | 2-way Intlv'ed | 2-way Intlv'ed | + | +-----------------------------+-----------------------------+ + | | 4-way Intlv'ed | + +--------------+-----------------------------------------------------------+ + + +Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ ====================================================== +-------------+---------------------------------------------------------+ | | Rank Interleaving | @@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode # superbank setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" + # 1KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB" + + # 4KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB" + + # 8KB 3-way interleaving + setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB" + # disable bank (chip-select) interleaving setenv hwconfig "fsl_ddr:bank_intlv=null" @@ -71,6 +103,11 @@ The ways to configure the ddr interleaving mode # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + # bank(chip-select) interleaving (auto) + setenv hwconfig "fsl_ddr:bank_intlv=auto" + This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings + on DIMMs. + Memory controller address hashing ================================== If the DDR controller supports address hashing, it can be enabled by hwconfig. @@ -222,3 +259,172 @@ Single slot system Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf + +Interactive DDR debugging +=========================== + +For DDR parameter tuning up and debugging, the interactive DDR debugger can +be activated by setting the environment variable "ddr_interactive" to any +value. (The value of ddr_interactive may have a meaning in the future, but, +for now, the presence of the variable will cause the debugger to run.) Once +activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR +controller. The available commands are printed by typing "help". + +Another way to enter the interactive DDR debugger without setting the +environment variable is to send the 'd' character early during the boot +process. To save booting time, no additional delay is added, so the window +to send the key press is very short -- basically, it is the time before the +memory controller code starts to run. For example, when rebooting from +within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to +initiate a 'reset' command. In case of power on/reset, the user can hold +down the 'd' key while applying power or hitting the board's reset button. + +The example flow of using interactive debugging is +type command "compute" to calculate the parameters from the default +type command "print" with arguments to show SPD, options, registers +type command "edit" with arguments to change any if desired +type command "copy" with arguments to copy controller/dimm settings +type command "go" to continue calculation and enable DDR controller + +Additional commands to restart the debugging are: +type command "reset" to reset the board +type command "recompute" to reload SPD and start over + +Note, check "next_step" to show the flow. For example, after edit opts, the +next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is +STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the +DDR controller with the current setting without further calculation and then +exit to resume the booting of the machine. + +The detail syntax for each commands are + +print [c] [d] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] + c - the controller number, eg. c0, c1 + d - the DIMM number, eg. d0, d1 + spd - print SPD data + dimmparms - DIMM parameters, calculated from SPD + commonparms - lowest common parameters for all DIMMs + opts - options + addresses - address assignment (not implemented yet) + regs - controller registers + +edit + c - the controller number, eg. c0, c1 + d - the DIMM number, eg. d0, d1 + spd - print SPD data + dimmparms - DIMM parameters, calculated from SPD + commonparms - lowest common parameters for all DIMMs + opts - options + addresses - address assignment (not implemented yet) + regs - controller registers + - name of the modified element + byte number if the object is SPD + - decimal or heximal (prefixed with 0x) numbers + +copy + same as for "edit" command + DIMM numbers ignored for commonparms, opts, and regs + +reset + no arguement - reset the board + +recompute + no argument - reload SPD and start over + +compute + no argument - recompute from current next_step + +next_step + no argument - show current next_step + +help + no argument - print a list of all commands + +go + no argument - program memory controller(s) and continue with U-boot + +Examples of debugging flow + + FSL DDR>compute + Detected UDIMM UG51U6400N8SU-ACF + FSL DDR>print + print [c] [d] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] + FSL DDR>print dimmparms + DIMM parameters: Controller=0 DIMM=0 + DIMM organization parameters: + module part name = UG51U6400N8SU-ACF + rank_density = 2147483648 bytes (2048 megabytes) + capacity = 4294967296 bytes (4096 megabytes) + burst_lengths_bitmask = 0C + base_addresss = 0 (00000000 00000000) + n_ranks = 2 + data_width = 64 + primary_sdram_width = 64 + ec_sdram_width = 0 + registered_dimm = 0 + n_row_addr = 15 + n_col_addr = 10 + edc_config = 0 + n_banks_per_sdram_device = 8 + tCKmin_X_ps = 1500 + tCKmin_X_minus_1_ps = 0 + tCKmin_X_minus_2_ps = 0 + tCKmax_ps = 0 + caslat_X = 960 + tAA_ps = 13125 + caslat_X_minus_1 = 0 + caslat_X_minus_2 = 0 + caslat_lowest_derated = 0 + tRCD_ps = 13125 + tRP_ps = 13125 + tRAS_ps = 36000 + tWR_ps = 15000 + tWTR_ps = 7500 + tRFC_ps = 160000 + tRRD_ps = 6000 + tRC_ps = 49125 + refresh_rate_ps = 7800000 + tIS_ps = 0 + tIH_ps = 0 + tDS_ps = 0 + tDH_ps = 0 + tRTP_ps = 7500 + tDQSQ_max_ps = 0 + tQHS_ps = 0 + FSL DDR>edit c0 opts ECC_mode 0 + FSL DDR>edit c0 regs cs0_bnds 0x000000FF + FSL DDR>go + 2 GiB left unmapped + 4 GiB (DDR3, 64-bit, CL=9, ECC off) + DDR Chip-Select Interleaving Mode: CS0+CS1 + Testing 0x00000000 - 0x7fffffff + Testing 0x80000000 - 0xffffffff + Remap DDR 2 GiB left unmapped + + POST memory PASSED + Flash: 128 MiB + L2: 128 KB enabled + Corenet Platform Cache: 1024 KB enabled + SERDES: timeout resetting bank 3 + SRIO1: disabled + SRIO2: disabled + MMC: FSL_ESDHC: 0 + EEPROM: Invalid ID (ff ff ff ff) + PCIe1: disabled + PCIe2: Root Complex, x1, regs @ 0xfe201000 + 01:00.0 - 8086:10d3 - Network controller + PCIe2: Bus 00 - 01 + PCIe3: disabled + In: serial + Out: serial + Err: serial + Net: Initializing Fman + Fman1: Uploading microcode version 101.8.0 + e1000: 00:1b:21:81:d2:e0 + FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME] + Warning: e1000#0 MAC addresses don't match: + Address in SROM is 00:1b:21:81:d2:e0 + Address in environment is 00:e0:0c:00:ea:05 + + Hit any key to stop autoboot: 0 + =>