X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fserial.c;h=60712b151e294c65e5b16e6a8f6e75ed0f228179;hb=d61ea14885631e58a25feaa81ee82eb464c62d6a;hp=2c77338f213b6e5c9281703e1477ae85a46f9fe3;hpb=ba56f625767d058b0e05a22729de13be5e0f6334;p=platform%2Fkernel%2Fu-boot.git diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 2c77338..60712b1 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -41,17 +41,26 @@ * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ /*------------------------------------------------------------------------------- */ - +/* + * Travis Sawyer 15 September 2004 + * Added CONFIG_SERIAL_MULTI support + */ #include #include #include #include #include "vecnum.h" -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO #include #endif +DECLARE_GLOBAL_DATA_PTR; + /*****************************************************************************/ #ifdef CONFIG_IOP480 @@ -147,7 +156,6 @@ #define asyncXOFFchar 0x13 #define asyncXONchar 0x11 - /* * Minimal serial functions needed to use one of the SMC ports * as serial console interface. @@ -155,8 +163,6 @@ int serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile char val; unsigned short br_reg; @@ -177,11 +183,8 @@ int serial_init (void) return (0); } - void serial_setbrg (void) { - DECLARE_GLOBAL_DATA_PTR; - unsigned short br_reg; br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); @@ -190,7 +193,6 @@ void serial_setbrg (void) out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ } - void serial_putc (const char c) { if (c == '\n') @@ -208,7 +210,6 @@ void serial_putc (const char c) } } - void serial_puts (const char *s) { while (*s) { @@ -216,7 +217,6 @@ void serial_puts (const char *s) } } - int serial_getc () { unsigned char status = 0; @@ -240,7 +240,6 @@ int serial_getc () return (0x000000ff & (int) in8 (asyncRxBufferport1)); } - int serial_tstc () { unsigned char status; @@ -264,23 +263,54 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ - /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) #if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#else #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 -#if defined(CONFIG_440_GX) -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#else +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GP) #define CR0_MASK 0x3fff0000 #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 -#endif /* CONFIG_440_GX */ -#elif defined(CONFIG_405EP) +#define UDIV_SUBTRACT 1 +#define UART0_SDR cntrl0 +#define MFREG(a, d) d = mfdcr(a) +#define MTREG(a, d) mtdcr(a, d) +#else /* #if defined(CONFIG_440GP) */ +/* all other 440 PPC's access clock divider via sdr register */ +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPe) +#define UART2_SDR sdr_uart2 +#endif +#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRx) +#define UART3_SDR sdr_uart3 +#endif +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) +#endif /* #if defined(CONFIG_440GP) */ +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f @@ -301,21 +331,19 @@ int serial_tstc () #if defined(CONFIG_UART1_CONSOLE) #define ACTING_UART0_BASE UART1_BASE #define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440_GX) -#define UART0_SDR sdr_uart1 -#define UART1_SDR sdr_uart0 -#endif /* CONFIG_440_GX */ #else #define ACTING_UART0_BASE UART0_BASE #define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440_GX) -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 -#endif /* CONFIG_440_GX */ +#endif + +#if defined(CONFIG_SERIAL_MULTI) +#define UART_BASE dev_base +#else +#define UART_BASE ACTING_UART0_BASE #endif #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) -#error "External serial clock not supported on IBM PPC405EP!" +#error "External serial clock not supported on AMCC PPC405EP!" #endif #define UART_RBR 0x00 @@ -350,8 +378,7 @@ int serial_tstc () /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO /*-----------------------------------------------------------------------------+ | Fifo +-----------------------------------------------------------------------------*/ @@ -364,53 +391,104 @@ typedef struct { volatile static serial_buffer_t buf_info; #endif - #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv ) + unsigned short *pbdiv) { - sys_info_t sysinfo; + sys_info_t sysinfo; unsigned long div; /* total divisor udiv * bdiv */ unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ unsigned long i; - unsigned long est; /* current estimate */ + unsigned long est; /* current estimate */ - get_sys_info( &sysinfo ); + get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ /* i is the test udiv value -- start with the largest * possible (32) to minimize serial clock and constrain * search to umin. */ - for( i = 32; i > umin; i-- ){ - ibdiv = div/i; + for (i = 32; i > umin; i--) { + ibdiv = div / i; est = i * ibdiv; idiff = (est > div) ? (est-div) : (div-est); - if( idiff == 0 ){ + if (idiff == 0) { udiv = i; break; /* can't do better */ - } - else if( idiff < diff ){ + } else if (idiff < diff) { udiv = i; /* best so far */ diff = idiff; /* update lowest diff*/ } } *pudiv = udiv; - *pbdiv = div/udiv; - + *pbdiv = div / udiv; } -#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ +#elif defined(CONFIG_405EZ) + +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + unsigned long plloutb; + unsigned long cpr_pllc; + u32 reg; + + /* check the pll feedback source */ + mfcpr(cprpllc, cpr_pllc); + + get_sys_info(&sysinfo); + + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + sysinfo.pllFwdDivB); + udiv = 256; /* Assume lowest possible serial clk */ + div = plloutb / (16 * baudrate); /* total divisor */ + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ + diff = 256; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (256) to minimize serial clock and constrain + * search to umin. + */ + for (i = 256; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + mfcpr(cprperd0, reg); + reg &= ~0x0000ffff; + reg |= ((udiv - 0) << 8) | (udiv - 0); + mtcpr(cprperd0, reg); + *pbdiv = div / udiv; +} +#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ /* * Minimal serial functions needed to use one of the SMC ports @@ -418,10 +496,12 @@ static void serial_divs (int baudrate, unsigned long *pudiv, */ #if defined(CONFIG_440) -int serial_init (void) +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init(void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - unsigned long reg; unsigned long udiv; unsigned short bdiv; @@ -430,12 +510,9 @@ int serial_init (void) unsigned long tmp; #endif -#if defined(CONFIG_440_GX) - mfsdr(UART0_SDR,reg); + MFREG(UART0_SDR, reg); reg &= ~CR0_MASK; -#else - reg = mfdcr(cntrl0) & ~CR0_MASK; -#endif /* CONFIG_440_GX */ + #ifdef CFG_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; @@ -449,33 +526,45 @@ int serial_init (void) serial_divs (gd->baudrate, &udiv, &bdiv); #endif -#if defined(CONFIG_440_GX) - reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ - mtsdr (UART0_SDR,reg); -#else - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); +#endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); #endif - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif + + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ return (0); } #else /* !defined(CONFIG_440) */ +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else int serial_init (void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - unsigned long reg; unsigned long tmp; unsigned long clk; @@ -483,6 +572,10 @@ int serial_init (void) unsigned short bdiv; volatile char val; +#if defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else #ifdef CONFIG_405EP reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; @@ -513,82 +606,83 @@ int serial_init (void) reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); #endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; - - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif /* CONFIG_405EZ */ + + out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8(UART_BASE + UART_LSR); /* clear line status */ + val = in8(UART_BASE + UART_RBR); /* read receive buffer */ + out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ return (0); } #endif /* if defined(CONFIG_440) */ +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else void serial_setbrg (void) +#endif { - DECLARE_GLOBAL_DATA_PTR; - - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - -#ifdef CFG_EXT_SERIAL_CLOCK - clk = CFG_EXT_SERIAL_CLOCK; +#if defined(CONFIG_SERIAL_MULTI) + serial_init_dev(dev_base); #else - clk = gd->cpu_clk; + serial_init(); #endif - -#ifdef CONFIG_405EP - udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); -#else - udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; - - out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ - out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ } - +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else void serial_putc (const char c) +#endif { int i; if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else serial_putc ('\r'); +#endif /* check THRE bit, wait for transmiter available */ for (i = 1; i < 3500; i++) { - if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) + if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) break; udelay (100); } - out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ + out8 (UART_BASE + UART_THR, c); /* put character out */ } - +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else void serial_puts (const char *s) +#endif { while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else serial_putc (*s++); +#endif } } - -int serial_getc () +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc (void) +#endif { unsigned char status = 0; @@ -596,7 +690,7 @@ int serial_getc () #if defined(CONFIG_HW_WATCHDOG) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ #endif /* CONFIG_HW_WATCHDOG */ - status = in8 (ACTING_UART0_BASE + UART_LSR); + status = in8 (UART_BASE + UART_LSR); if ((status & asyncLSRDataReady1) != 0x0) { break; } @@ -604,22 +698,25 @@ int serial_getc () asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART0_BASE + UART_LSR, + out8 (UART_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); + return (0x000000ff & (int) in8 (UART_BASE)); } - -int serial_tstc () +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc (void) +#endif { unsigned char status; - status = in8 (ACTING_UART0_BASE + UART_LSR); + status = in8 (UART_BASE + UART_LSR); if ((status & asyncLSRDataReady1) != 0x0) { return (1); } @@ -627,7 +724,7 @@ int serial_tstc () asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART0_BASE + UART_LSR, + out8 (UART_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | @@ -636,8 +733,7 @@ int serial_tstc () return 0; } - -#if CONFIG_SERIAL_SOFTWARE_FIFO +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO void serial_isr (void *arg) { @@ -651,8 +747,8 @@ void serial_isr (void *arg) } else { space = rx_get - rx_put; } - while (serial_tstc ()) { - c = serial_getc (); + while (serial_tstc_dev (ACTING_UART0_BASE)) { + c = serial_getc_dev (ACTING_UART0_BASE); if (space) { buf_info.rx_buffer[rx_put++] = c; space--; @@ -752,8 +848,7 @@ int serial_buffered_tstc (void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 @@ -765,8 +860,6 @@ int serial_buffered_tstc (void) #if (CONFIG_KGDB_SER_INDEX & 2) void kgdb_serial_init (void) { - DECLARE_GLOBAL_DATA_PTR; - volatile char val; unsigned short br_reg; @@ -788,7 +881,6 @@ void kgdb_serial_init (void) out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ } - void putDebugChar (const char c) { if (c == '\n') @@ -800,7 +892,6 @@ void putDebugChar (const char c) while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); } - void putDebugStr (const char *s) { while (*s) { @@ -808,7 +899,6 @@ void putDebugStr (const char *s) } } - int getDebugChar (void) { unsigned char status = 0; @@ -832,7 +922,6 @@ int getDebugChar (void) return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); } - void kgdb_interruptible (int yes) { return; @@ -865,6 +954,89 @@ void kgdb_interruptible (int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ +#endif + + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(UART0_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(UART1_BASE)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(UART0_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(UART1_BASE); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(UART0_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(UART1_BASE, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(UART0_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(UART1_BASE, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(UART0_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(UART1_BASE)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(UART0_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(UART1_BASE)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ #endif /* CONFIG_405GP || CONFIG_405CR */