X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fndfc.c;h=72acfd01b5e6f685fc02fdfbfd5ebcad1a241605;hb=d3c23a790fb24f9cb5cc467b81b0c3ad3eeb1f96;hp=c255f93e6bba1cdf6470f728856bbce189ee6592;hpb=afa98843e4665add11b69496341053b268156e3a;p=platform%2Fkernel%2Fu-boot.git diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index c255f93..72acfd0 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -3,7 +3,7 @@ * Platform independend driver for NDFC (NanD Flash Controller) * integrated into EP440 cores * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Based on original work by @@ -31,75 +31,77 @@ #include -#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ +#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) #include #include +#include #include -#include +#include +#include -static u8 hwctl = 0; +/* + * We need to store the info, which chip-select (CS) is used for the + * chip number. For example on Sequoia NAND chip #0 uses + * CS #3. + */ +static int ndfc_cs[NDFC_MAX_BANKS]; -static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd) +static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - switch (cmd) { - case NAND_CTL_SETCLE: - hwctl |= 0x1; - break; - - case NAND_CTL_CLRCLE: - hwctl &= ~0x1; - break; - - case NAND_CTL_SETALE: - hwctl |= 0x2; - break; - - case NAND_CTL_CLRALE: - hwctl &= ~0x2; - break; - } + struct nand_chip *this = mtd->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF); + else + out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF); } -static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte) +static int ndfc_dev_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; - if (hwctl & 0x1) - out8(base + NDFC_CMD, byte); - else if (hwctl & 0x2) - out8(base + NDFC_ALE, byte); - else - out8(base + NDFC_DATA, byte); + return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); } -static u_char ndfc_read_byte(struct mtd_info *mtdinfo) +static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; + u32 ccr; - return (in8(base + NDFC_DATA)); + ccr = in_be32((u32 *)(base + NDFC_CCR)); + ccr |= NDFC_CCR_RESET_ECC; + out_be32((u32 *)(base + NDFC_CCR), ccr); } -static int ndfc_dev_ready(struct mtd_info *mtdinfo) +static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, + const u_char *dat, u_char *ecc_code) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; + u32 ecc; + u8 *p = (u8 *)&ecc; - while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY)) - ; + ecc = in_be32((u32 *)(base + NDFC_ECC)); - return 1; -} + /* The NDFC uses Smart Media (SMC) bytes order + */ + ecc_code[0] = p[1]; + ecc_code[1] = p[2]; + ecc_code[2] = p[3]; -#ifndef CONFIG_NAND_SPL -/* - * Don't use these speedup functions in NAND boot image, since the image - * has to fit into 4kByte. - */ + return 0; +} /* * Speedups for buffer read/write/verify @@ -110,66 +112,103 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo) */ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; uint32_t *p = (uint32_t *) buf; - for(;len > 0; len -= 4) - *p++ = in32(base + NDFC_DATA); + for (;len > 0; len -= 4) + *p++ = in_be32((u32 *)(base + NDFC_DATA)); } +#ifndef CONFIG_NAND_SPL +/* + * Don't use these speedup functions in NAND boot image, since the image + * has to fit into 4kByte. + */ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) - out32(base + NDFC_DATA, *p++); + for (; len > 0; len -= 4) + out_be32((u32 *)(base + NDFC_DATA), *p++); } static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) { - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) this->IO_ADDR_W; + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; uint32_t *p = (uint32_t *) buf; - for(; len > 0; len -= 4) - if (*p++ != in32(base + NDFC_DATA)) + for (; len > 0; len -= 4) + if (*p++ != in_be32((u32 *)(base + NDFC_DATA))) return -1; return 0; } #endif /* #ifndef CONFIG_NAND_SPL */ -void board_nand_init(struct nand_chip *nand) +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + /* + * Don't use "chip" to address the NAND device, + * generate the cs from the address where it is encoded. + */ + ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; + int cs = ndfc_cs[chip]; + + /* Set NandFlash Core Configuration Register */ + /* 1 col x 2 rows */ + out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); + out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222); +} + +int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + int cs = (ulong)nand->IO_ADDR_W & 0x00000003; + ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; + static int chip = 0; - nand->hwcontrol = ndfc_hwcontrol; - nand->read_byte = ndfc_read_byte; - nand->write_byte = ndfc_write_byte; - nand->dev_ready = ndfc_dev_ready; + /* + * Save chip-select for this chip # + */ + ndfc_cs[chip] = cs; + + /* + * Select required NAND chip in NDFC + */ + board_nand_select_device(nand, chip); + + nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA); + nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA); + nand->cmd_ctrl = ndfc_hwcontrol; + nand->chip_delay = 50; + nand->read_buf = ndfc_read_buf; + nand->dev_ready = ndfc_dev_ready; + nand->ecc.correct = nand_correct_data; + nand->ecc.hwctl = ndfc_enable_hwecc; + nand->ecc.calculate = ndfc_calculate_ecc; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 256; + nand->ecc.bytes = 3; #ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; - nand->read_buf = ndfc_read_buf; nand->verify_buf = ndfc_verify_buf; #else /* * Setup EBC (CS0 only right now) */ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtebc(EBC0_CFG, 0xb8400000); mtebc(pb0cr, CFG_EBC_PB0CR); mtebc(pb0ap, CFG_EBC_PB0AP); #endif - /* Set NandFlash Core Configuration Register */ - /* Chip select 3, 1col x 2 rows */ - out32(CFG_NAND_BASE + NDFC_CCR, 0x00000000 | (CFG_NAND_CS << 24)); - out32(CFG_NAND_BASE + NDFC_BCFG0 + (CFG_NAND_CS << 2), 0x80002222); + chip++; + + return 0; } #endif