X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fppc4xx%2Fcpu.c;h=22879046694e060ee06337d87ac5883eee21f928;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=06f44ad376fb7931e897f5562d30cd963314dd96;hpb=1bbae2b816d4ed38db2ebf42166a973b1ffc0df7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 06f44ad..2287904 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -54,6 +54,7 @@ int __get_cpu_num(void)
 }
 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
 
+#if defined(CONFIG_PCI)
 #if defined(CONFIG_405GP) || \
     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -63,7 +64,7 @@ int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
 static int pci_async_enabled(void)
 {
 #if defined(CONFIG_405GP)
-	return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
+	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
 #endif
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -71,32 +72,33 @@ static int pci_async_enabled(void)
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
-	mfsdr(sdr_sdstp1, val);
+	mfsdr(SDR0_SDSTP1, val);
 	return (val & SDR0_SDSTP1_PAME_MASK);
 #endif
 }
 #endif
+#endif /* CONFIG_PCI */
 
 #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
     !defined(CONFIG_405) && !defined(CONFIG_405EX)
 static int pci_arbiter_enabled(void)
 {
 #if defined(CONFIG_405GP)
-	return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
+	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
 #endif
 
 #if defined(CONFIG_405EP)
-	return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
+	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
 #endif
 
 #if defined(CONFIG_440GP)
-	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
+	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
 #endif
 
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long val;
 
-	mfsdr(sdr_xcr, val);
+	mfsdr(SDR0_XCR, val);
 	return (val & 0x80000000);
 #endif
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -104,7 +106,7 @@ static int pci_arbiter_enabled(void)
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	unsigned long val;
 
-	mfsdr(sdr_pci0, val);
+	mfsdr(SDR0_PCI0, val);
 	return (val & 0x80000000);
 #endif
 }
@@ -116,11 +118,11 @@ static int pci_arbiter_enabled(void)
 static int i2c_bootrom_enabled(void)
 {
 #if defined(CONFIG_405EP)
-	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
+	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
 #else
 	unsigned long val;
 
-	mfsdr(sdr_sdcs, val);
+	mfsdr(SDR0_SDCS0, val);
 	return (val & SDR0_SDCS_SDD);
 #endif
 }
@@ -254,7 +256,7 @@ static int bootstrap_option(void)
 {
 	unsigned long val;
 
-	mfsdr(SDR_PINSTP, val);
+	mfsdr(SDR0_PINSTP, val);
 	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 }
 #endif /* SDR0_PINSTP_SHIFT */
@@ -263,14 +265,14 @@ static int bootstrap_option(void)
 #if defined(CONFIG_440)
 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 {
-	/* Changes to cpc0_sys0 and cpc0_sys1 require chip
+	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
 	 * reset.
 	 */
-	mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000);	/* Set SWE */
-	mtdcr (cpc0_sys0, sys0);
-	mtdcr (cpc0_sys1, sys1);
-	mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000);	/* Clr SWE */
-	mtspr (dbcr0, 0x20000000);	/* Reset the chip */
+	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);	/* Set SWE */
+	mtdcr (CPC0_SYS0, sys0);
+	mtdcr (CPC0_SYS1, sys1);
+	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);	/* Clr SWE */
+	mtspr (SPRN_DBCR0, 0x20000000);	/* Reset the chip */
 
 	return 1;
 }
@@ -283,6 +285,9 @@ int checkcpu (void)
 	uint pvr = get_pvr();
 	ulong clock = gd->cpu_clk;
 	char buf[32];
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	u32 reg;
+#endif
 
 #if !defined(CONFIG_IOP480)
 	char addstr[64] = "";
@@ -405,13 +410,13 @@ int checkcpu (void)
 	case PVR_440GP_RB:
 		puts("GP Rev. B");
 		/* See errata 1.12: CHIP_4 */
-		if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
-		    (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
+		if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
+		    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
 			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 				"Resetting chip ...\n");
 			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
-			do_chip_reset ( mfdcr(cpc0_strp0),
-					mfdcr(cpc0_strp1) );
+			do_chip_reset ( mfdcr(CPC0_STRP0),
+					mfdcr(CPC0_STRP1) );
 		}
 		break;
 
@@ -524,6 +529,7 @@ int checkcpu (void)
 		strcpy(addstr, "No RAID 6 support");
 		break;
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 	case PVR_460EX_RA:
 		puts("EX Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
@@ -534,6 +540,15 @@ int checkcpu (void)
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
+	case PVR_460EX_RB:
+		puts("EX Rev. B");
+		mfsdr(SDR0_ECID3, reg);
+		if (reg & 0x00100000)
+			strcpy(addstr, "No Security/Kasumi support");
+		else
+			strcpy(addstr, "Security/Kasumi support");
+		break;
+
 	case PVR_460GT_RA:
 		puts("GT Rev. A");
 		strcpy(addstr, "No Security/Kasumi support");
@@ -544,6 +559,16 @@ int checkcpu (void)
 		strcpy(addstr, "Security/Kasumi support");
 		break;
 
+	case PVR_460GT_RB:
+		puts("GT Rev. B");
+		mfsdr(SDR0_ECID3, reg);
+		if (reg & 0x00100000)
+			strcpy(addstr, "No Security/Kasumi support");
+		else
+			strcpy(addstr, "Security/Kasumi support");
+		break;
+#endif
+
 	case PVR_460SX_RA:
 		puts("SX Rev. A");
 		strcpy(addstr, "Security support");
@@ -652,12 +677,12 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	board_reset();
 #else
 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
-	mtspr(dbcr0, CONFIG_SYS_4xx_RESET_TYPE << 28);
+	mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 #else
 	/*
 	 * Initiate system reset in debug control register DBCR
 	 */
-	mtspr(dbcr0, 0x30000000);
+	mtspr(SPRN_DBCR0, 0x30000000);
 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 #endif /* defined(CONFIG_BOARD_RESET) */
 
@@ -695,7 +720,7 @@ void reset_4xx_watchdog(void)
 	/*
 	 * Clear TSR(WIS) bit
 	 */
-	mtspr(tsr, 0x40000000);
+	mtspr(SPRN_TSR, 0x40000000);
 }
 #endif	/* CONFIG_WATCHDOG */