X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fppc4xx%2F4xx_pci.c;h=e97f32c7b0781c823c7d55e908b210861f67598b;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=c28c7ac86dd64e440ea4e3e601e13ec2f2dfc684;hpb=1a247ba7fa5fb09f56892a09a990f03ce564b3e2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index c28c7ac..e97f32c 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -1,4 +1,6 @@
 /*-----------------------------------------------------------------------------+
+ *       This source code is dual-licensed.  You may use it under the terms of
+ *       the GNU General Public license version 2, or under the license below.
  *
  *       This source code has been made available to you by IBM on an AS-IS
  *       basis.  Anyone receiving this source is licensed under IBM
@@ -87,6 +89,20 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int __pci_pre_init(struct pci_controller *hose)
 {
+#if defined (CONFIG_405EP)
+	/*
+	 * Enable the internal PCI arbiter by default.
+	 *
+	 * On 405EP CPUs the internal arbiter can be controlled
+	 * by the I2C strapping EEPROM. If you want to do so
+	 * or if you want to disable the arbiter pci_pre_init()
+	 * must be reimplemented without enabling the arbiter.
+	 * The arbiter is enabled in this place because of
+	 * compatibility reasons.
+	 */
+	mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
+#endif /* CONFIG_405EP */
+
 	return 1;
 }
 int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
@@ -99,6 +115,19 @@ ushort pmc405_pci_subsys_deviceid(void);
 
 /*#define DEBUG*/
 
+int __is_pci_host(struct pci_controller *hose)
+{
+#if defined(CONFIG_405GP)
+	if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
+		return 1;
+#elif defined (CONFIG_405EP)
+	if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
+		return 1;
+#endif
+	return 0;
+}
+int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
+
 /*-----------------------------------------------------------------------------+
  * pci_init.  Initializes the 405GP PCI Configuration regs.
  *-----------------------------------------------------------------------------*/
@@ -108,12 +137,12 @@ void pci_405gp_init(struct pci_controller *hose)
 	bd_t *bd = gd->bd;
 
 	unsigned short temp_short;
-	unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
-#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+	unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
+#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
 	char *ptmla_str, *ptmms_str;
 #endif
-	unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
-	unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
+	unsigned long ptmla[2]    = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
+	unsigned long ptmms[2]    = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 	unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 	unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
@@ -131,7 +160,7 @@ void pci_405gp_init(struct pci_controller *hose)
 #endif
 #endif
 
-#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
+#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
 	ptmla_str = getenv("ptm1la");
 	ptmms_str = getenv("ptm1ms");
 	if(NULL != ptmla_str && NULL != ptmms_str ) {
@@ -179,7 +208,7 @@ void pci_405gp_init(struct pci_controller *hose)
 				       ptmpcila[i], ptmla[i],
 				       ~(ptmms[i] & 0xfffff000) + 1,
 				       PCI_REGION_MEM |
-				       PCI_REGION_MEMORY);
+				       PCI_REGION_SYS_MEMORY);
 		}
 
 	/* PCI memory spaces */
@@ -268,25 +297,25 @@ void pci_405gp_init(struct pci_controller *hose)
 	/*
 	 * Insert Subsystem Vendor and Device ID
 	 */
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
 #ifdef CONFIG_CPCI405
-	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+	if (is_pci_host(hose))
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 	else
-		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
+		pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
 #else
-	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
+	pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 #endif
 
 	/*
 	 * Insert Class-code
 	 */
-#ifdef CFG_PCI_CLASSCODE
-	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
-#endif /* CFG_PCI_CLASSCODE */
+#ifdef CONFIG_SYS_PCI_CLASSCODE
+	pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
+#endif /* CONFIG_SYS_PCI_CLASSCODE */
 
 	/*--------------------------------------------------------------------------+
-	 * If PCI speed = 66Mhz, set 66Mhz capable bit.
+	 * If PCI speed = 66MHz, set 66MHz capable bit.
 	 *--------------------------------------------------------------------------*/
 	if (bd->bi_pci_busfreq >= 66000000) {
 		pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
@@ -295,7 +324,7 @@ void pci_405gp_init(struct pci_controller *hose)
 
 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
-	if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+	if (is_pci_host(hose) ||
 	    (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
 	{
@@ -310,8 +339,15 @@ void pci_405gp_init(struct pci_controller *hose)
 	}
 #endif
 
-#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
-	pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
+#if defined(CONFIG_405EP)
+	/*
+	 * on ppc405ep vendor/device id is not set
+	 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
+	 * are the correct values.
+	 */
+	pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
+	pci_write_config_word(PCIDEVID_405GP,
+			      PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
 #endif
 
 	/*
@@ -325,7 +361,7 @@ void pci_405gp_init(struct pci_controller *hose)
 	 * Scan the PCI bus and configure devices found.
 	 *--------------------------------------------------------------------------*/
 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
-	if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) ||
+	if (is_pci_host(hose) ||
 	    (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
 #endif
 	{
@@ -405,8 +441,8 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
  */
 static struct pci_config_table pci_405gp_config_table[] = {
 /*if VendID is 0 it terminates the table search (ie Walnut)*/
-#ifdef CFG_PCI_SUBSYS_VENDORID
-	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
+#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
+	{CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 #endif
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
@@ -455,7 +491,7 @@ int pci_440_init (struct pci_controller *hose)
 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 	unsigned long strap;
 
-	mfsdr(sdr_sdstp1,strap);
+	mfsdr(SDR0_SDSTP1,strap);
 	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
 		printf("PCI: SDR0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
@@ -464,7 +500,7 @@ int pci_440_init (struct pci_controller *hose)
 #elif defined(CONFIG_440GP)
 	unsigned long strap;
 
-	strap = mfdcr(cpc0_strp1);
+	strap = mfdcr(CPC0_STRP1);
 	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
 		printf("PCI: CPC0_STRP1[PISE] not set.\n");
 		printf("PCI: Configuration aborted.\n");
@@ -488,10 +524,10 @@ int pci_440_init (struct pci_controller *hose)
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + reg_num++,
-		       CFG_PCI_TARGBASE,
-		       CFG_PCI_MEMBASE,
-#ifdef CFG_PCI_MEMSIZE
-		       CFG_PCI_MEMSIZE,
+		       CONFIG_SYS_PCI_TARGBASE,
+		       CONFIG_SYS_PCI_MEMBASE,
+#ifdef CONFIG_SYS_PCI_MEMSIZE
+		       CONFIG_SYS_PCI_MEMSIZE,
 #else
 		       0x10000000,
 #endif
@@ -504,7 +540,7 @@ int pci_440_init (struct pci_controller *hose)
 		       CONFIG_PCI_SYS_MEM_BUS,
 		       CONFIG_PCI_SYS_MEM_PHYS,
 		       CONFIG_PCI_SYS_MEM_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY );
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
 #endif
 
 	hose->region_count = reg_num;
@@ -523,11 +559,11 @@ int pci_440_init (struct pci_controller *hose)
 	/*--------------------------------------------------------------------------+
 	 * PCI target init
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_SYS_PCI_TARGET_INIT)
 	pci_target_init(hose);                /* Let board setup pci target */
 #else
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
 	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 #endif
 
@@ -542,23 +578,25 @@ int pci_440_init (struct pci_controller *hose)
 
 	/*--------------------------------------------------------------------------+
 	 * PCI master init: default is one 256MB region for PCI memory:
-	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
+	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
 	 *--------------------------------------------------------------------------*/
-#if defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_SYS_PCI_MASTER_INIT)
 	pci_master_init(hose);          /* Let board setup pci master */
 #else
 	out32r( PCIX0_POM0SA, 0 ); /* disable */
 	out32r( PCIX0_POM1SA, 0 ); /* disable */
 	out32r( PCIX0_POM2SA, 0 ); /* disable */
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SPE)
 	out32r( PCIX0_POM0LAL, 0x10000000 );
 	out32r( PCIX0_POM0LAH, 0x0000000c );
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	out32r( PCIX0_POM0LAL, 0x20000000 );
+	out32r( PCIX0_POM0LAH, 0x0000000c );
 #else
 	out32r( PCIX0_POM0LAL, 0x00000000 );
 	out32r( PCIX0_POM0LAH, 0x00000003 );
 #endif
-	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
+	out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
 	out32r( PCIX0_POM0PCIAH, 0x00000000 );
 	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
@@ -588,8 +626,9 @@ void pci_init_board(void)
 	int busno;
 
 	busno = pci_440_init (&ppc440_hose);
-#if defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if (defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
+    !defined(CONFIG_PCI_DISABLE_PCIE)
 	pcie_setup_hoses(busno + 1);
 #endif
 }