X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Fspd_sdram.c;h=e26db7c3bf59083587c7fb3b9a6891859f6468db;hb=1730edf76c54381475e2da11f75b1ce563c4e62c;hp=e501caf457af39dc4864bd84e24182fbbf8d737c;hpb=746c4b9490495dc4381dbcc49f40078d423e0a48;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index e501caf..e26db7c 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -528,7 +528,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 			caslat -= 1;
 		else if (busfreq > max_data_rate) {
 			printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
-		     	busfreq, max_data_rate);
+			busfreq, max_data_rate);
 			return 0;
 		}
 	}
@@ -644,8 +644,8 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num,
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0
@@ -943,7 +943,7 @@ unsigned int enable_ddr(unsigned int ddr_num)
 	spd_eeprom_t spd1,spd2;
 	volatile ccsr_ddr_t *ddr;
 	unsigned sdram_cfg_1;
-	unsigned char sdram_type, mem_type, config, mod_attr;
+	unsigned char sdram_type, mem_type, mod_attr;
 	unsigned char d_init;
 	unsigned int no_dimm1=0, no_dimm2=0;
 
@@ -1017,6 +1017,10 @@ unsigned int enable_ddr(unsigned int ddr_num)
 		printf("No memory modules found for DDR controller %d!!\n", ddr_num);
 		return 0;
 	} else {
+
+#if defined(CONFIG_DDR_ECC)
+		unsigned char config;
+#endif
 		mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
 
 		/*
@@ -1122,8 +1126,8 @@ spd_sdram(void)
 	int memsize_ddr1_dimm2 = 0;
 	int memsize_ddr1 = 0;
 	unsigned int law_size_ddr1;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 #ifdef CONFIG_DDR_INTERLEAVE
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
 	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
 #endif
 
@@ -1179,11 +1183,10 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 1 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+		set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
 #endif
 		debug("Interleaved memory size is 0x%08lx\n", memsize_total);
 
-#ifdef	CONFIG_DDR_INTERLEAVE
 #if (CFG_PAGE_INTERLEAVING == 1)
 		printf("Page ");
 #elif (CFG_BANK_INTERLEAVING == 1)
@@ -1193,7 +1196,6 @@ spd_sdram(void)
 #else
 		printf("Cache-line ");
 #endif
-#endif
 		printf("Interleaved");
 		return memsize_total * 1024 * 1024;
 	}  else {
@@ -1236,7 +1238,7 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 1 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+		set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
 #endif
 	}
 
@@ -1263,7 +1265,7 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 2 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(8,
+		set_next_law(
 			(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
 			law_size_ddr2, LAW_TRGT_IF_DDR_2);
 #endif