X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc86xx%2Fspd_sdram.c;h=e26db7c3bf59083587c7fb3b9a6891859f6468db;hb=1730edf76c54381475e2da11f75b1ce563c4e62c;hp=5cc0c266f06ce9cd62cd1894a3c1958226fee236;hpb=9d2459f3532c009bb903b02b57079a3862420a5f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 5cc0c26..e26db7c 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -1183,7 +1183,7 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 1 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+		set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
 #endif
 		debug("Interleaved memory size is 0x%08lx\n", memsize_total);
 
@@ -1238,7 +1238,7 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 1 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+		set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
 #endif
 	}
 
@@ -1265,7 +1265,7 @@ spd_sdram(void)
 		 * Set up LAWBAR for DDR 2 space.
 		 */
 #ifdef CONFIG_FSL_LAW
-		set_law(8,
+		set_next_law(
 			(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
 			law_size_ddr2, LAW_TRGT_IF_DDR_2);
 #endif