X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fspd_sdram.c;h=8e321eb07320fc3133c8179afb6b49bdc5951f3a;hb=1730edf76c54381475e2da11f75b1ce563c4e62c;hp=abc63c414bd70a3f937906262b84718151bc65e6;hpb=e57ed96baca1222e6cd3d7032691a89d5890bb4a;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index abc63c4..8e321eb 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -306,7 +306,7 @@ spd_sdram(void)
 	 * Adjust DDR II IO voltage biasing.
 	 * Only 8548 rev 1 needs the fix
 	 */
-	if ((SVR_VER(get_svr()) == SVR_8548_E) &&
+	if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) &&
 			(SVR_MJREV(get_svr()) == 1) &&
 			(spd.mem_type == SPD_MEMTYPE_DDR2)) {
 		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
@@ -610,8 +610,8 @@ spd_sdram(void)
 	/*
 	 * Sneak in some Extended Refresh Recovery.
 	 */
-	ddr->ext_refrec = (trfc_high << 16);
-	debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
+	ddr->timing_cfg_3 = (trfc_high << 16);
+	debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 
 	ddr->timing_cfg_1 =
 	    (0
@@ -1090,7 +1090,7 @@ setup_laws_and_tlbs(unsigned int memsize)
 	 */
 
 #ifdef CONFIG_FSL_LAW
-	set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
+	set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
 #endif
 
 	/*