X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Frelease.S;h=433ff0254487fd4bdede65a08cd8d88ed89f5790;hb=06f43286c6354aaab0103615e83893512f86eee7;hp=a1ae78a7f55f35b1f08f772f65e17fdbadf88810;hpb=d187fcaaa24399068ca04d7f3f9b56fdde3fc3f0;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index a1ae78a..433ff02 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -102,18 +102,22 @@ __secondary_start_page:
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* Enable/invalidate the L2 cache */
 	msync
-	lis	r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
-	ori	r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
-	mtspr	SPRN_L2CSR0,r3
+	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
+	ori	r2,r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
+	mtspr	SPRN_L2CSR0,r2
 1:
 	mfspr	r3,SPRN_L2CSR0
-	andis.	r1,r3,L2CSR0_L2FI@h
+	and.	r1,r3,r2
 	bne	1b
 
 	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
 	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
 	mtspr	SPRN_L2CSR0,r3
 	isync
+2:
+	mfspr	r3,SPRN_L2CSR0
+	andis.	r1,r3,L2CSR0_L2E@h
+	beq	2b
 #endif
 
 #define EPAPR_MAGIC		(0x45504150)