X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc85xx%2Fcpu_init.c;h=736aef17256873ad1c6f9999a2da3e9f5457cbbe;hb=1730edf76c54381475e2da11f75b1ce563c4e62c;hp=9517146ed23deeeb46708d60f27ec05a2b5673ea;hpb=256176d3d5462d466e2c8434281ced50257c8add;p=platform%2Fkernel%2Fu-boot.git diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 9517146..736aef1 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,4 +1,6 @@ /* + * Copyright 2007 Freescale Semiconductor. + * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com * @@ -29,12 +31,38 @@ #include #include #include +#include +#include +#include "mp.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_QE +extern qe_iop_conf_t qe_iop_conf_tab[]; +extern void qe_config_iopin(u8 port, u8 pin, int dir, + int open_drain, int assign); +extern void qe_init(uint qe_base); +extern void qe_reset(void); + +static void config_qe_ioports(void) +{ + u8 port, pin; + int dir, open_drain, assign; + int i; + + for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { + port = qe_iop_conf_tab[i].port; + pin = qe_iop_conf_tab[i].pin; + dir = qe_iop_conf_tab[i].dir; + open_drain = qe_iop_conf_tab[i].open_drain; + assign = qe_iop_conf_tab[i].assign; + qe_config_iopin(port, pin, dir, open_drain, assign); + } +} +#endif #ifdef CONFIG_CPM2 -static void config_8560_ioports (volatile immap_t * immr) +void config_8560_ioports (volatile ccsr_cpm_t * cpm) { int portnum; @@ -74,7 +102,7 @@ static void config_8560_ioports (volatile immap_t * immr) } if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (immr, portnum); + volatile ioport_t *iop = ioport_addr (cpm, portnum); uint tpmsk = ~pmsk; /* @@ -97,6 +125,40 @@ static void config_8560_ioports (volatile immap_t * immr) } #endif +/* We run cpu_init_early_f in AS = 1 */ +void cpu_init_early_f(void) +{ + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 0, BOOKE_PAGESZ_4K, 0); + + /* set up CCSR if we want it moved */ +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) + { + u32 temp; + + set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 1, 1, BOOKE_PAGESZ_4K, 0); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); + + temp = in_be32((volatile u32 *)CFG_CCSRBAR); + } +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + init_laws(); + invalidate_tlb(0); + init_tlbs(); +} + /* * Breathe some life into the CPU... * @@ -106,19 +168,14 @@ static void config_8560_ioports (volatile immap_t * immr) void cpu_init_f (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_lbc_t *memctl = &immap->im_lbc; + volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); extern void m8560_cpm_reset (void); - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - + disable_tlb(14); + disable_tlb(15); #ifdef CONFIG_CPM2 - config_8560_ioports(immap); + config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary @@ -133,15 +190,18 @@ void cpu_init_f (void) #endif /* now restrict to preliminary range */ + /* if cs1 is already set via debugger, leave cs0/cs1 alone */ + if (! memctl->br1 & 1) { #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; #endif + } #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; @@ -176,6 +236,11 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif +#ifdef CONFIG_QE + /* Config QE ioports */ + config_qe_ioports(); +#endif + } @@ -185,52 +250,78 @@ void cpu_init_f (void) * The newer 8548, etc, parts have twice as much cache, but * use the same bit-encoding as the older 8555, etc, parts. * - * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? */ int cpu_init_r(void) { + puts ("L2: "); + #if defined(CONFIG_L2_CACHE) - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; uint svr, ver; + uint l2srbar; svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; switch (cache_ctl & 0x30000000) { case 0x20000000: - if (ver == SVR_8548 || ver == SVR_8548_E) { - printf ("L2 cache 512KB:"); + if (ver == SVR_8548 || ver == SVR_8548_E || + ver == SVR_8544 || ver == SVR_8568_E) { + puts ("512 KB "); + /* set L2E=1, L2I=1, & L2SRAM=0 */ + cache_ctl = 0xc0000000; } else { - printf ("L2 cache 256KB:"); + puts("256 KB "); + /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ + cache_ctl = 0xc8000000; } break; - case 0x00000000: case 0x10000000: + puts("256 KB "); + if (ver == SVR_8544 || ver == SVR_8544_E) { + cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ + } + break; case 0x30000000: + case 0x00000000: default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + printf(" unknown size (0x%08x)\n", cache_ctl); return -1; } - asm("msync;isync"); - l2cache->l2ctl = 0x68000000; /* invalidate */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ - cache_ctl = l2cache->l2ctl; - asm("msync;isync"); - - printf(" enabled\n"); + if (l2cache->l2ctl & 0x80000000) { + puts("already enabled"); + l2srbar = l2cache->l2srbar0; +#ifdef CFG_INIT_L2_ADDR + if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { + l2srbar = CFG_INIT_L2_ADDR; + l2cache->l2srbar0 = l2srbar; + printf("moving to 0x%08x", CFG_INIT_L2_ADDR); + } +#endif /* CFG_INIT_L2_ADDR */ + puts("\n"); + } else { + asm("msync;isync"); + l2cache->l2ctl = cache_ctl; /* invalidate & enable */ + asm("msync;isync"); + puts("enabled\n"); + } #else - printf("L2 cache: disabled\n"); + puts("disabled\n"); +#endif +#ifdef CONFIG_QE + uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ + qe_init(qe_base); + qe_reset(); #endif +#if defined(CONFIG_MP) + setup_mp(); +#endif return 0; }