X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Fmpc824x%2Fcpu_init.c;h=395f7767d124fc6ba2aa3830da9c313e43590c7d;hb=6d0f6bcf337c5261c08fabe12982178c2c489d76;hp=7871031b9709610ac9fa805992b1260af8172902;hpb=71edc271816ec82cf0550dd6980be2da3cc2ad9e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c
index 7871031..395f776 100644
--- a/cpu/mpc824x/cpu_init.c
+++ b/cpu/mpc824x/cpu_init.c
@@ -25,32 +25,32 @@
 #include <asm/processor.h>
 #include <mpc824x.h>
 
-#ifndef CFG_BANK0_ROW
-#define CFG_BANK0_ROW 0
+#ifndef CONFIG_SYS_BANK0_ROW
+#define CONFIG_SYS_BANK0_ROW 0
 #endif
-#ifndef CFG_BANK1_ROW
-#define CFG_BANK1_ROW 0
+#ifndef CONFIG_SYS_BANK1_ROW
+#define CONFIG_SYS_BANK1_ROW 0
 #endif
-#ifndef CFG_BANK2_ROW
-#define CFG_BANK2_ROW 0
+#ifndef CONFIG_SYS_BANK2_ROW
+#define CONFIG_SYS_BANK2_ROW 0
 #endif
-#ifndef CFG_BANK3_ROW
-#define CFG_BANK3_ROW 0
+#ifndef CONFIG_SYS_BANK3_ROW
+#define CONFIG_SYS_BANK3_ROW 0
 #endif
-#ifndef CFG_BANK4_ROW
-#define CFG_BANK4_ROW 0
+#ifndef CONFIG_SYS_BANK4_ROW
+#define CONFIG_SYS_BANK4_ROW 0
 #endif
-#ifndef CFG_BANK5_ROW
-#define CFG_BANK5_ROW 0
+#ifndef CONFIG_SYS_BANK5_ROW
+#define CONFIG_SYS_BANK5_ROW 0
 #endif
-#ifndef CFG_BANK6_ROW
-#define CFG_BANK6_ROW 0
+#ifndef CONFIG_SYS_BANK6_ROW
+#define CONFIG_SYS_BANK6_ROW 0
 #endif
-#ifndef CFG_BANK7_ROW
-#define CFG_BANK7_ROW 0
+#ifndef CONFIG_SYS_BANK7_ROW
+#define CONFIG_SYS_BANK7_ROW 0
 #endif
-#ifndef CFG_DBUS_SIZE2
-#define CFG_DBUS_SIZE2 0
+#ifndef CONFIG_SYS_DBUS_SIZE2
+#define CONFIG_SYS_DBUS_SIZE2 0
 #endif
 
 /*
@@ -163,150 +163,150 @@ cpu_init_f (void)
 #endif
 	CONFIG_WRITE_WORD(PICR2, val);
 
-	CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
-#ifndef CFG_RAMBOOT
-	CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
-				 (CFG_BANK0_ROW) |
-				 (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
-				 (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
-				 (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
-				 (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
-				 (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
-				 (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
-				 (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
-				 (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
+	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
+#ifndef CONFIG_SYS_RAMBOOT
+	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
+				 (CONFIG_SYS_BANK0_ROW) |
+				 (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
+				 (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
+				 (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
+				 (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
+				 (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
+				 (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
+				 (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
+				 (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
 #endif
 
-#if defined(CFG_ASRISE) && defined(CFG_ASFALL)
-	CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
-				 CFG_ASRISE << MCCR2_ASRISE_SHIFT |
-				 CFG_ASFALL << MCCR2_ASFALL_SHIFT);
+#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
+	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
+				 CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
+				 CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
 #else
-	CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
 #endif
 
 #if defined(CONFIG_MPC8240)
 	CONFIG_WRITE_WORD(MCCR3,
-		(((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
-		(CFG_REFREC << MCCR3_REFREC_SHIFT) |
-		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT));
+		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
 #elif defined(CONFIG_MPC8245)
 	CONFIG_WRITE_WORD(MCCR3,
-		(((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
-		(CFG_REFREC << MCCR3_REFREC_SHIFT));
+		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
 #else
 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
 
 /* this is gross.  We think these should all be the same, and various boards
- *  should define CFG_ACTORW to 0 if they don't want to set it, or even, if
+ *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
  *  its not set, we define it to zero in this file
  */
 #if defined(CONFIG_CU824) || defined(CONFIG_PN62)
 	CONFIG_WRITE_WORD(MCCR4,
-	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-	(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 	MCCR4_BIT21 |
-	(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-	((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-	(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
-		  CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
-	(CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
-	(((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
+	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
+		  CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
+	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
+	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
 #elif defined(CONFIG_MPC8240)
 	CONFIG_WRITE_WORD(MCCR4,
-	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-	(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
 	MCCR4_BIT21 |
-	(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-	((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-	(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
-		  (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
-	(((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
+		  (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
+	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 #elif defined(CONFIG_MPC8245)
 	CONFIG_READ_WORD(MCCR1, val);
 	val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */
 
 	CONFIG_WRITE_WORD(MCCR4,
-		(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
-		(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
-		(CFG_EXTROM ? MCCR4_EXTROM : 0) |
-		(CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
-		(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
-		((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
-		(CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
-		(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
+		(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+		(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+		(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
+		(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+		((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+		(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
+		(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
 		      (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
-		(CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
-		(((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+		(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
+		(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
 #else
 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 #endif
 
 	CONFIG_WRITE_WORD(MSAR1,
-		( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(EMSAR1,
-		( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(MSAR2,
-		( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(EMSAR2,
-		( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(MEAR1,
-		( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(EMEAR1,
-		( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(MEAR2,
-		( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
-		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
-		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
-		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+		( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
 	CONFIG_WRITE_WORD(EMEAR2,
-		( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
-		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
-		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
-		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-
-	CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
-#ifdef CFG_DLL_MAX_DELAY
-	CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY);	/* needed to make DLL lock */
+		( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+
+	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
+#ifdef CONFIG_SYS_DLL_MAX_DELAY
+	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);	/* needed to make DLL lock */
 #endif
-#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
-	CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
+#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
+	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
 #endif
-#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
-	CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD);	/* change memory input */
+#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
+	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);	/* change memory input */
 #endif /* setup & hold time */
 
 	CONFIG_WRITE_BYTE(MBER,
-		 CFG_BANK0_ENABLE |
-		(CFG_BANK1_ENABLE << 1) |
-		(CFG_BANK2_ENABLE << 2) |
-		(CFG_BANK3_ENABLE << 3) |
-		(CFG_BANK4_ENABLE << 4) |
-		(CFG_BANK5_ENABLE << 5) |
-		(CFG_BANK6_ENABLE << 6) |
-		(CFG_BANK7_ENABLE << 7));
-
-#ifdef CFG_PGMAX
-	CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
+		 CONFIG_SYS_BANK0_ENABLE |
+		(CONFIG_SYS_BANK1_ENABLE << 1) |
+		(CONFIG_SYS_BANK2_ENABLE << 2) |
+		(CONFIG_SYS_BANK3_ENABLE << 3) |
+		(CONFIG_SYS_BANK4_ENABLE << 4) |
+		(CONFIG_SYS_BANK5_ENABLE << 5) |
+		(CONFIG_SYS_BANK6_ENABLE << 6) |
+		(CONFIG_SYS_BANK7_ENABLE << 7));
+
+#ifdef CONFIG_SYS_PGMAX
+	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
 #endif
 
 	/* ! Wait 200us before initialize other registers */