X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2Farm920t%2Fstart.S;h=779f192e519ef000fef340722aabffe30382417c;hb=35e3717772c8c3534c18d8aac69e4b822777c23b;hp=74a97d52903db7396f1172f0808a0776968326ea;hpb=b304c96871c92d1ec8fa57dda36cc198660fd10e;p=platform%2Fkernel%2Fu-boot.git diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 74a97d5..779f192 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -3,7 +3,7 @@ * * Copyright (c) 2001 Marius Gröger * Copyright (c) 2002 Alex Züpke - * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2002 Gary Jennejohn * * See file CREDITS for list of people who contributed to this * project. @@ -24,10 +24,8 @@ * MA 02111-1307 USA */ - +#include #include -#include - /* ************************************************************************* @@ -39,7 +37,7 @@ .globl _start -_start: b reset +_start: b start_code ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -62,7 +60,7 @@ _fiq: .word fiq /* ************************************************************************* * - * Startup Code (reset vector) + * Startup Code (called from the ARM reset exception vector) * * do important init only if we don't start from memory! * relocate armboot to ram @@ -104,34 +102,52 @@ FIQ_STACK_START: /* - * the actual reset code + * the actual start code */ -reset: +start_code: /* * set the cpu to SVC32 mode */ - mrs r0,cpsr - bic r0,r0,#0x1f - orr r0,r0,#0xd3 - msr cpsr,r0 - -/* turn off the watchdog */ -#if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ -#elif defined(CONFIG_S3C2410) -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr, r0 + + bl coloured_LED_init + bl red_LED_on + +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) + /* + * relocate exception table + */ + ldr r0, =_start + ldr r1, =0x0 + mov r2, #16 +copyex: + subs r2, r2, #1 + ldr r3, [r0], #4 + str r3, [r1], #4 + bne copyex #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] +#ifdef CONFIG_S3C24X0 + /* turn off the watchdog */ + +# if defined(CONFIG_S3C2400) +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define CLKDIVN 0x14800014 /* clock divisor register */ +#else +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTSUBMSK 0x4A00001C +# define CLKDIVN 0x4C000014 /* clock divisor register */ +# endif + + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] /* * mask all IRQs by setting all bits in the INTMR - default @@ -150,7 +166,7 @@ reset: ldr r0, =CLKDIVN mov r1, #3 str r1, [r0] -#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ +#endif /* CONFIG_S3C24X0 */ /* * we do sys-critical inits only at reboot, @@ -164,8 +180,8 @@ reset: relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ - cmp r0, r1 /* don't reloc during debug */ - beq stack_setup + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup ldr r2, _armboot_start ldr r3, _bss_start @@ -182,8 +198,8 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ - sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ - sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ + sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif @@ -192,34 +208,13 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l -#if 0 - /* try doing this stuff after the relocation */ - ldr r0, =pWTCON - mov r1, #0x0 - str r1, [r0] - - /* - * mask all IRQs by setting all bits in the INTMR - default - */ - mov r1, #0xffffffff - ldr r0, =INTMR - str r1, [r0] - - /* FCLK:HCLK:PCLK = 1:2:4 */ - /* default FCLK is 120 MHz ! */ - ldr r0, =CLKDIVN - mov r1, #3 - str r1, [r0] - /* END stuff after relocation */ -#endif - ldr pc, _start_armboot _start_armboot: .word start_armboot @@ -237,6 +232,7 @@ _start_armboot: .word start_armboot */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -255,18 +251,18 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 - /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will * find a lowlevel_init.S in your board directory. */ mov ip, lr + bl lowlevel_init - mov lr, ip + mov lr, ip mov pc, lr - +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ /* ************************************************************************* @@ -301,8 +297,8 @@ cpu_init_crit: #define S_R1 4 #define S_R0 0 -#define MODE_SVC 0x13 -#define I_BIT 0x80 +#define MODE_SVC 0x13 +#define I_BIT 0x80 /* * use bad_save_user_regs for abort/prefetch/undef/swi ... @@ -313,8 +309,10 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 ldr r2, _armboot_start - sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + sub r2, r2, #(CONFIG_STACKSIZE) + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) + /* set base 2 words into abort stack */ + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -327,12 +325,12 @@ cpu_init_crit: .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC - mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 + add r7, sp, #S_PC + stmdb r7, {sp, lr}^ @ Calling SP, LR + str lr, [r7, #0] @ Save calling PC + mrs r6, spsr + str r6, [r7, #4] @ Save CPSR + str r0, [r7, #8] @ Save OLD_R0 mov r0, sp .endm @@ -341,17 +339,20 @@ cpu_init_crit: mov r0, r0 ldr lr, [sp, #S_PC] @ Get PC add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr + /* return & move spsr_svc into cpsr */ + subs pc, lr, #4 .endm .macro get_bad_stack ldr r13, _armboot_start @ setup our mode stack - sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN) - sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack + sub r13, r13, #(CONFIG_STACKSIZE) + sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) + /* reserve a couple spots in abort stack */ + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) str lr, [r13] @ save caller lr / spsr mrs lr, spsr - str lr, [r13, #4] + str lr, [r13, #4] mov r13, #MODE_SVC @ prepare SVC-Mode @ msr spsr_c, r13 @@ -375,31 +376,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -407,7 +408,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -415,7 +416,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -424,12 +425,12 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif