X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=cpu%2FChangeLog;h=375cb199669a5ee8d8ce7c51ff5007a9a0a93380;hb=0231a51ef7ff49336d3a2f0e4eec09cd17b23c95;hp=3e01aea5c61a46b5441de6cf61902e5c0522a463;hpb=72f4393d8cfc4a47f0e59657f7822668cfad132f;p=external%2Fbinutils.git diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 3e01aea..375cb19 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,170 @@ +2019-09-09 Phil Blundell + + binutils 2.33 branch created. + +2019-07-19 Jose E. Marchesi + + * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of + %a and %ctx. + +2019-07-15 Jose E. Marchesi + + * bpf.cpu (dlabs): New pmacro. + (dlind): Likewise. + +2019-07-14 Jose E. Marchesi + + * bpf.cpu (dlsi): ldabs and ldind instructions do not take an + explicit 'dst' argument. + +2019-06-13 Stafford Horne + + * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol. + +2019-06-13 Stafford Horne + + * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a + (l-adrp): Improve comment. + +2019-06-13 Stafford Horne + + * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S, + SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D, + SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes. + (float-setflag-insn-base): New pmacro based on float-setflag-insn. + (float-setflag-symantics, float-setflag-unordered-cmp-symantics, + float-setflag-unordered-symantics): New pmacro for instruction + symantics. + (float-setflag-insn): Update to use float-setflag-insn-base. + (float-setflag-unordered-insn): New pmacro for generating instructions. + +2019-06-13 Andrey Bacherov + Stafford Horne + + * or1k.cpu (ORFPX64A32-MACHS): New pmacro. + (ORFPX-MACHS): Removed pmacro. + * or1k.opc (or1k_cgen_insn_supported): New function. + (CGEN_VALIDATE_INSN_SUPPORTED): Define macro. + (parse_regpair, print_regpair): New functions. + * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder + and add comments. + (h-fdr): Update comment to indicate or64. + (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs. + (h-fd32r): New hardware for 64-bit fpu registers. + (h-i64r): New hardware for 64-bit int registers. + * or1korbis.cpu (f-resv-8-1): New field. + * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS. + (rDDF, rADF, rBDF): Update operand comment to indicate or64. + (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields. + (h-roff1): New hardware. + (double-field-and-ops mnemonic): New pmacro to generate operations + rDD32F, rAD32F, rBD32F, rDDI and rADI. + (float-regreg-insn): Update single precision generator to MACH + ORFPX32-MACHS. Add generator for or32 64-bit instructions. + (float-setflag-insn): Update single precision generator to MACH + ORFPX32-MACHS. Fix double instructions from single to double + precision. Add generator for or32 64-bit instructions. + (float-cust-insn cust-num): Update single precision generator to MACH + ORFPX32-MACHS. Add generator for or32 64-bit instructions. + (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to + ORFPX32-MACHS. + (lf-rem-d): Fix operation from mod to rem. + (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction. + (lf-itof-d): Fix operands from single to double. + (lf-ftoi-d): Update operand mode from DI to WI. + +2019-05-23 Jose E. Marchesi + + * bpf.cpu: New file. + * bpf.opc: Likewise. + +2018-06-24 Nick Clifton + + 2.32 branch created. + +2018-10-05 Richard Henderson + Stafford Horne + + * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU. + (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU. + (l-mul): Fix overflow support and indentation. + (l-mulu): Fix overflow support and indentation. + (l-muld, l-muldu, l-msbu, l-macu): New instructions. + (l-div); Remove incorrect carry behavior. + (l-divu): Fix carry and overflow behavior. + (l-mac): Add overflow support. + (l-msb, l-msbu): Add carry and overflow support. + +2018-10-05 Richard Henderson + + * or1k.opc (parse_disp26): Add support for plta() relocations. + (parse_disp21): New function. + (or1k_rclass): New enum. + (or1k_rtype): New enum. + (or1k_imm16_relocs): Define new PO and SPO relocation mappings. + (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. + (parse_imm16): Add support for the new 21bit and 13bit relocations. + * or1korbis.cpu (f-disp26): Don't assume SI. + (f-disp21): New pc-relative 21-bit 13 shifted to right. + (insn-opcode): Add ADRP. + (l-adrp): New instruction. + +2018-10-05 Richard Henderson + + * or1k.opc: Add RTYPE_ enum. + (INVALID_STORE_RELOC): New string. + (or1k_imm16_relocs): New array array. + (parse_reloc): New static function that just does the parsing. + (parse_imm16): New static function for generic parsing. + (parse_simm16): Change to just call parse_imm16. + (parse_simm16_split): New function. + (parse_uimm16): Change to call parse_imm16. + (parse_uimm16_split): New function. + * or1korbis.cpu (simm16-split): Change to use new simm16_split. + (uimm16-split): Change to use new uimm16_split. + +2018-07-24 Alan Modra + + PR 23430 + * or1kcommon.cpu (spr-reg-indices): Fix description typo. + +2018-05-09 Sebastian Rasmussen + + * or1kcommon.cpu (spr-reg-info): Typo fix. + +2018-03-03 Alan Modra + + * frv.opc: Include opintl.h. + (add_next_to_vliw): Use opcodes_error_handler to print error. + Standardize error message. + (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. + +2018-01-13 Nick Clifton + + 2.30 branch created. + +2017-03-15 Stafford Horne + + * or1kcommon.cpu: Add pc set semantics to also update ppc. + +2016-10-06 Alan Modra + + * mep.opc (expand_string): Add fall through comment. + +2016-03-03 Alan Modra + + * fr30.cpu (f-m4): Replace bogus comment with a better guess + at what is really going on. + +2016-03-02 Alan Modra + + * fr30.cpu (f-m4): Replace -1 << 4 with -16. + +2016-02-02 Andrew Burgess + + * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to + a constant to better align disassembler output. + 2014-07-20 Stefan Kristiansson * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.