X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=configs%2FT2080RDB_revD_SPIFLASH_defconfig;h=a03b211f73e8a77e7f78a12e86c410bb1a2328c1;hb=cdcbd593ad9a2111eaebad63f020b6c756cd9b8b;hp=4c6879b7a5d19be9aadc415b9be18d3088e532fa;hpb=296d5cffdd08298cb41fb82122f29f4c329df569;p=platform%2Fkernel%2Fu-boot.git

diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 4c6879b..a03b211 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -9,11 +9,11 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
 CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
-CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_T2080RDB_REV_D=y
@@ -21,17 +21,21 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_RAMBOOT_PBL=y
+CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
+CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg"
 CONFIG_BOOTDELAY=10
 CONFIG_BOARD_EARLY_INIT_R=y
 # CONFIG_SPL_FRAMEWORK is not set
 CONFIG_SPL_SPI_BOOT=y
 CONFIG_SPL_FSL_PBL=y
 CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_MPC8XXX_INIT_DDR=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_IMLS=y
+CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 CONFIG_CMD_DM=y
@@ -53,7 +57,21 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_DDR_CLK_FREQ=133330000
+CONFIG_DDR_ECC=y
+CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_FSL=y
+CONFIG_SYS_FSL_I2C_OFFSET=0x118000
+CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
+CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
+CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
+CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
+CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
+CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
 CONFIG_FSL_ESDHC=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
@@ -62,20 +80,19 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=10000000
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_AQUANTIA=y
 CONFIG_PHY_CORTINA=y
 CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
+CONFIG_CORTINA_FW_ADDR=0x120000
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_MDIO=y
 CONFIG_E1000=y
 CONFIG_FMAN_ENET=y
 CONFIG_MII=y
-CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCIE_FSL=y
 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
@@ -86,7 +103,6 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_ESPI=y
 CONFIG_USB=y
-CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_ADDR_MAP=y
 CONFIG_SYS_NUM_ADDR_MAP=64