X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=common%2Ffdt_support.c;h=5aa8e3422e8de71c1fb4efa057bd187356e32a46;hb=98f705c9cefdfdba62c069821bbba10273a0a8ed;hp=c6a76b7ad299f365d08542ed7f583f8f1f2720ea;hpb=797f165f7ae90a75579ae3df7932d8d1518e8544;p=platform%2Fkernel%2Fu-boot.git diff --git a/common/fdt_support.c b/common/fdt_support.c index c6a76b7..5aa8e34 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -642,84 +642,6 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) { } #endif -#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE -/* - * Provide a weak default function to return the flash bank size. - * There might be multiple non-identical flash chips connected to one - * chip-select, so we need to pass an index as well. - */ -u32 __flash_get_bank_size(int cs, int idx) -{ - extern flash_info_t flash_info[]; - - /* - * As default, a simple 1:1 mapping is provided. Boards with - * a different mapping need to supply a board specific mapping - * routine. - */ - return flash_info[cs].size; -} -u32 flash_get_bank_size(int cs, int idx) - __attribute__((weak, alias("__flash_get_bank_size"))); - -/* - * This function can be used to update the size in the "reg" property - * of all NOR FLASH device nodes. This is necessary for boards with - * non-fixed NOR FLASH sizes. - */ -int fdt_fixup_nor_flash_size(void *blob) -{ - char compat[][16] = { "cfi-flash", "jedec-flash" }; - int off; - int len; - struct fdt_property *prop; - u32 *reg, *reg2; - int i; - - for (i = 0; i < 2; i++) { - off = fdt_node_offset_by_compatible(blob, -1, compat[i]); - while (off != -FDT_ERR_NOTFOUND) { - int idx; - - /* - * Found one compatible node, so fixup the size - * int its reg properties - */ - prop = fdt_get_property_w(blob, off, "reg", &len); - if (prop) { - int tuple_size = 3 * sizeof(reg); - - /* - * There might be multiple reg-tuples, - * so loop through them all - */ - reg = reg2 = (u32 *)&prop->data[0]; - for (idx = 0; idx < (len / tuple_size); idx++) { - /* - * Update size in reg property - */ - reg[2] = flash_get_bank_size(reg[0], - idx); - - /* - * Point to next reg tuple - */ - reg += 3; - } - - fdt_setprop(blob, off, "reg", reg2, len); - } - - /* Move to next compatible node */ - off = fdt_node_offset_by_compatible(blob, off, - compat[i]); - } - } - - return 0; -} -#endif - int fdt_increase_size(void *fdt, int add_len) { int newlen; @@ -1008,7 +930,7 @@ struct of_bus { }; /* Default translator (generic bus) */ -void of_bus_default_count_cells(const void *blob, int parentoffset, +void fdt_support_default_count_cells(const void *blob, int parentoffset, int *addrc, int *sizec) { const fdt32_t *prop; @@ -1030,9 +952,9 @@ static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range, { u64 cp, s, da; - cp = of_read_number(range, na); - s = of_read_number(range + na + pna, ns); - da = of_read_number(addr, na); + cp = fdt_read_number(range, na); + s = fdt_read_number(range + na + pna, ns); + da = fdt_read_number(addr, na); debug("OF: default map, cp=%" PRIu64 ", s=%" PRIu64 ", da=%" PRIu64 "\n", cp, s, da); @@ -1044,7 +966,7 @@ static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range, static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na) { - u64 a = of_read_number(addr, na); + u64 a = fdt_read_number(addr, na); memset(addr, 0, na * 4); a += offset; if (na > 1) @@ -1086,9 +1008,9 @@ static u64 of_bus_isa_map(fdt32_t *addr, const fdt32_t *range, if ((addr[0] ^ range[0]) & cpu_to_be32(1)) return OF_BAD_ADDR; - cp = of_read_number(range + 1, na - 1); - s = of_read_number(range + na + pna, ns); - da = of_read_number(addr + 1, na - 1); + cp = fdt_read_number(range + 1, na - 1); + s = fdt_read_number(range + na + pna, ns); + da = fdt_read_number(addr + 1, na - 1); debug("OF: ISA map, cp=%" PRIu64 ", s=%" PRIu64 ", da=%" PRIu64 "\n", cp, s, da); @@ -1122,7 +1044,7 @@ static struct of_bus of_busses[] = { { .name = "default", .addresses = "reg", - .count_cells = of_bus_default_count_cells, + .count_cells = fdt_support_default_count_cells, .map = of_bus_default_map, .translate = of_bus_default_translate, }, @@ -1173,7 +1095,7 @@ static int of_translate_one(const void *blob, int parent, struct of_bus *bus, */ ranges = fdt_getprop(blob, parent, rprop, &rlen); if (ranges == NULL || rlen == 0) { - offset = of_read_number(addr, na); + offset = fdt_read_number(addr, na); memset(addr, 0, pna * 4); debug("OF: no ranges, 1:1 translation\n"); goto finish; @@ -1253,7 +1175,7 @@ static u64 __of_translate_address(const void *blob, int node_offset, /* If root, we have finished */ if (parent < 0) { debug("OF: reached root node\n"); - result = of_read_number(addr, na); + result = fdt_read_number(addr, na); break; } @@ -1539,7 +1461,7 @@ int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr) /* * Returns the base address of an SOC or PCI node */ -u64 fdt_get_base_address(void *fdt, int node) +u64 fdt_get_base_address(const void *fdt, int node) { int size; u32 naddr; @@ -1666,8 +1588,8 @@ int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width, fdt32_t cells[4]; int i, addrc, sizec, ret; - of_bus_default_count_cells(fdt, fdt_parent_offset(fdt, node), - &addrc, &sizec); + fdt_support_default_count_cells(fdt, fdt_parent_offset(fdt, node), + &addrc, &sizec); i = 0; if (addrc == 2) cells[i++] = cpu_to_fdt32(base_address >> 32);