X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ftqc%2Ftqma6%2Ftqma6.c;h=816672edc6b808849a5772534dcc893fbc04566e;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=b552bb8d7eee1ff099a973bb2e1e9bfff61c4e32;hpb=7f14fb20f895016fb38d30ce71aeb4d441b5bcb8;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c index b552bb8..816672e 100644 --- a/board/tqc/tqma6/tqma6.c +++ b/board/tqc/tqma6/tqma6.c @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. * Author: Fabio Estevam * * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) * Author: Markus Niebel - * - * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -13,17 +12,19 @@ #include #include #include -#include +#include #include #include -#include +#include +#include #include #include -#include +#include #include #include #include #include +#include #include "tqma6_bb.h" @@ -45,12 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } @@ -75,7 +76,7 @@ static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = { /* * According to board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 eMMC (SD3) on TQMa6 * mmc1 .. n optional slots used on baseboard */ @@ -138,11 +139,13 @@ static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = { NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL), }; +#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19) + static unsigned const tqma6_ecspi1_cs[] = { - IMX_GPIO_NR(3, 19), + TQMA6_SF_CS_GPIO, }; -static void tqma6_iomuxc_spi(void) +__weak void tqma6_iomuxc_spi(void) { unsigned i; @@ -152,6 +155,12 @@ static void tqma6_iomuxc_spi(void) ARRAY_SIZE(tqma6_ecspi1_pads)); } +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return ((bus == CONFIG_SF_DEFAULT_BUS) && + (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1; +} + static struct i2c_pads_info tqma6_i2c3_pads = { /* I2C3: on board LM75, M24C64, */ .scl = { @@ -172,8 +181,14 @@ static struct i2c_pads_info tqma6_i2c3_pads = { static void tqma6_setup_i2c(void) { - /* use logical index for bus, e.g. I2C1 -> 0 */ - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + int ret; + /* + * use logical index for bus, e.g. I2C1 -> 0 + * warn on error + */ + ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); + if (ret) + printf("setup I2C3 failed: %d\n", ret); } int board_early_init_f(void) @@ -216,25 +231,27 @@ static const char *tqma6_get_boardname(void) }; } -int board_late_init(void) +/* setup board specific PMIC */ +int power_init_board(void) { struct pmic *p; - u32 reg; + u32 reg, rev; - setenv("board_name", tqma6_get_boardname()); - - /* - * configure PFUZE100 PMIC: - * TODO: should go to power_init_board if bus switching is - * fixed in generic power code - */ power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { pmic_reg_read(p, PFUZE100_DEVICEID, ®); - printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + pmic_reg_read(p, PFUZE100_REVID, &rev); + printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); } + return 0; +} + +int board_late_init(void) +{ + env_set("board_name", tqma6_get_boardname()); + tqma6_bb_board_late_init(); return 0; @@ -251,12 +268,21 @@ int checkboard(void) * Device Tree Support */ #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -void ft_board_setup(void *blob, bd_t *bd) +#define MODELSTRLEN 32u +int ft_board_setup(void *blob, bd_t *bd) { + char modelstr[MODELSTRLEN]; + + snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(), + tqma6_bb_get_boardname()); + do_fixup_by_path_string(blob, "/", "model", modelstr); + fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size); /* bring in eMMC dsr settings */ do_fixup_by_path_u32(blob, "/soc/aips-bus@02100000/usdhc@02198000", "dsr", tqma6_emmc_dsr, 2); tqma6_bb_ft_board_setup(blob, bd); + + return 0; } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */