X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ftqc%2Ftqm5200%2Ftqm5200.c;h=c48ab11fc41922c19d481756295793ef6c52056f;hb=4125bbcef6a998ce8580a1f5c53c8c93a56a125b;hp=f9891dbb74fb4c717216e074ca9fbb2e197bf6ff;hpb=32d4e38eeb5bcc2f854787bfa68bea2b55eaa1d7;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index f9891db..c48ab11 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -8,30 +8,17 @@ * (C) Copyright 2004-2006 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include #include #include #include +#include +#include #ifdef CONFIG_VIDEO_SM501 #include @@ -53,7 +40,49 @@ DECLARE_GLOBAL_DATA_PTR; void ps2mult_early_init(void); #endif -#ifndef CFG_RAMBOOT +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \ + defined(CONFIG_VIDEO) +/* + * EDID block has been generated using Phoenix EDID Designer 1.3. + * This tool creates a text file containing: + * + * EDID BYTES: + * + * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F + * ------------------------------------------------ + * 00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00 + * 10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00 + * 20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01 + * 30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00 + * 40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00 + * 50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 + * 60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 + * 70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17 + * + * Then this data has been manually converted to the char + * array below. + */ +static unsigned char edid_buf[128] = { + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, + 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, +}; +#endif + +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -99,18 +128,18 @@ static void sdram_start (int hi_addr) #endif /* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * ATTENTION: Although partially referenced dram_init does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ -long int initdram (int board_type) +int dram_init(void) { ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -131,9 +160,9 @@ long int initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -160,10 +189,10 @@ long int initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); } if (test1 > test2) { sdram_start(0); @@ -185,7 +214,7 @@ long int initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -202,7 +231,7 @@ long int initdram (int board_type) } else { dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -223,19 +252,16 @@ long int initdram (int board_type) } #if defined(CONFIG_TQM5200_B) - return dramsize + dramsize2; + gd->ram_size = dramsize + dramsize2; #else - return dramsize; + gd->ram_size = dramsize; #endif /* CONFIG_TQM5200_B */ + + return 0; } int checkboard (void) { -#if defined(CONFIG_AEVFIFO) - puts ("Board: AEVFIFO\n"); - return 0; -#endif - #if defined(CONFIG_TQM5200S) # define MODULE_NAME "TQM5200S" #else @@ -244,12 +270,12 @@ int checkboard (void) #if defined(CONFIG_STK52XX) # define CARRIER_NAME "STK52xx" -#elif defined(CONFIG_TB5200) -# define CARRIER_NAME "TB5200" #elif defined(CONFIG_CAM5200) # define CARRIER_NAME "CAM5200" #elif defined(CONFIG_FO300) # define CARRIER_NAME "FO300" +#elif defined(CONFIG_CHARON) +# define CARRIER_NAME "CHARON" #else # error "UNKNOWN" #endif @@ -357,11 +383,9 @@ int post_hotkeys_pressed(void) gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. + * Configure PSC6_0 through PSC6_3 as GPIO. */ - gpio->port_config &= ~(0x07000000); - gpio->port_config |= 0x03000000; + gpio->port_config &= ~(0x00700000); /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ gpio->simple_gpioe |= 0x20000000; @@ -376,25 +400,6 @@ int post_hotkeys_pressed(void) } #endif -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - -void post_word_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - - *save_addr = a; -} - -ulong post_word_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - - return *save_addr; -} -#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { @@ -405,7 +410,7 @@ int board_early_init_r (void) ps2mult_early_init(); #endif /* CONFIG_PS2MULT */ -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) /* Low level USB init, required for proper kernel operation */ usb_cpu_init(); #endif @@ -449,6 +454,101 @@ int board_early_init_f (void) } #endif /* CONFIG_FO300 */ +#if defined(CONFIG_CHARON) +#include +#include + +/* The TFP410 registers */ +#define TFP410_REG_VEN_ID_L 0x00 +#define TFP410_REG_VEN_ID_H 0x01 +#define TFP410_REG_DEV_ID_L 0x02 +#define TFP410_REG_DEV_ID_H 0x03 +#define TFP410_REG_REV_ID 0x04 + +#define TFP410_REG_CTL_1_MODE 0x08 +#define TFP410_REG_CTL_2_MODE 0x09 +#define TFP410_REG_CTL_3_MODE 0x0A + +#define TFP410_REG_CFG 0x0B + +#define TFP410_REG_DE_DLY 0x32 +#define TFP410_REG_DE_CTL 0x33 +#define TFP410_REG_DE_TOP 0x34 +#define TFP410_REG_DE_CNT_L 0x36 +#define TFP410_REG_DE_CNT_H 0x37 +#define TFP410_REG_DE_LIN_L 0x38 +#define TFP410_REG_DE_LIN_H 0x39 + +#define TFP410_REG_H_RES_L 0x3A +#define TFP410_REG_H_RES_H 0x3B +#define TFP410_REG_V_RES_L 0x3C +#define TFP410_REG_V_RES_H 0x3D + +static int tfp410_read_reg(int reg, uchar *buf) +{ + puts("Error reading the chip.\n"); + return -ENOSYS; +} + +static int tfp410_write_reg(int reg, uchar buf) +{ + puts("Error writing the chip.\n"); + return -ENOSYS; +} + +typedef struct _tfp410_config { + int reg; + uchar val; +}TFP410_CONFIG; + +static TFP410_CONFIG tfp410_configtbl[] = { + {TFP410_REG_CTL_1_MODE, 0x37}, + {TFP410_REG_CTL_2_MODE, 0x20}, + {TFP410_REG_CTL_3_MODE, 0x80}, + {TFP410_REG_DE_DLY, 0x90}, + {TFP410_REG_DE_CTL, 0x00}, + {TFP410_REG_DE_TOP, 0x23}, + {TFP410_REG_DE_CNT_H, 0x02}, + {TFP410_REG_DE_CNT_L, 0x80}, + {TFP410_REG_DE_LIN_H, 0x01}, + {TFP410_REG_DE_LIN_L, 0xe0}, + {-1, 0}, +}; + +static int charon_last_stage_init(void) +{ + volatile struct mpc5xxx_lpb *lpb = + (struct mpc5xxx_lpb *) MPC5XXX_LPB; + uchar buf; + int i = 0; + + /* check version */ + if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0) + return -1; + if (!(buf & 0x04)) + return -1; + if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0) + return -1; + if (!(buf & 0x10)) + return -1; + /* OK, now init the chip */ + while (tfp410_configtbl[i].reg != -1) { + int ret; + + ret = tfp410_write_reg(tfp410_configtbl[i].reg, + tfp410_configtbl[i].val); + if (ret != 0) + return -1; + i++; + } + printf("TFP410 initialized.\n"); + + /* set deadcycle for cs3 to 0 */ + setbits_be32(&lpb->cs_deadcycle, 0xffffcfff); + return 0; +} +#endif + int last_stage_init (void) { /* @@ -463,34 +563,34 @@ int last_stage_init (void) */ /* save original SRAM content */ - save = *(volatile u16 *)CFG_CS2_START; + save = *(volatile u16 *)CONFIG_SYS_CS2_START; restore = 1; /* write test pattern to SRAM */ - *(volatile u16 *)CFG_CS2_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in SRAM detection\n"); - if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { /* no SRAM at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; restore = 0; __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { /* make sure that we access a mirrored address */ - *(volatile u16 *)CFG_CS2_START = 0x1111; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; __asm__ volatile ("sync"); - if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, 0x80000); __asm__ volatile ("sync"); puts ("SRAM: 512 kB\n"); @@ -502,7 +602,7 @@ int last_stage_init (void) } /* restore origianl SRAM content */ if (restore) { - *(volatile u16 *)CFG_CS2_START = save; + *(volatile u16 *)CONFIG_SYS_CS2_START = save; __asm__ volatile ("sync"); } @@ -512,21 +612,21 @@ int last_stage_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; @@ -538,7 +638,7 @@ int last_stage_init (void) } /* restore origianl FB content */ if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } @@ -550,6 +650,9 @@ int last_stage_init (void) #endif #endif /* !CONFIG_TQM5200S */ +#if defined(CONFIG_CHARON) + charon_last_stage_init(); +#endif return 0; } @@ -645,14 +748,15 @@ void video_get_info_str (int line_number, char *info) { if (line_number == 1) { strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); -#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300) +#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \ + defined(CONFIG_STK52XX) } else if (line_number == 2) { +#if defined (CONFIG_CHARON) + strcpy (info, " on a CHARON carrier board"); +#endif #if defined (CONFIG_STK52XX) strcpy (info, " on a STK52xx carrier board"); #endif -#if defined (CONFIG_TB5200) - strcpy (info, " on a TB5200 carrier board"); -#endif #if defined (CONFIG_FO300) strcpy (info, " on a FO300 carrier board"); #endif @@ -678,21 +782,21 @@ unsigned int board_video_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller found */ restore = 0; ret = 0; @@ -701,7 +805,7 @@ unsigned int board_video_init (void) } if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } return ret; @@ -743,9 +847,29 @@ int board_get_height (void) #endif /* CONFIG_VIDEO_SM501 */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +#if defined(CONFIG_VIDEO) + fdt_add_edid(blob, "smi,sm501", edid_buf); +#endif + + return 0; } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_RESET_PHY_R) +#include + +void reset_phy(void) +{ + /* init Micrel KSZ8993 PHY */ + miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09); +} +#endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +}