X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fti%2Fks2_evm%2Fboard.c;h=1683f780a33b646ca67a466e5ae54273fe2cded6;hb=65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8;hp=c61baeeb8cf5d76093160db0408caf48120a71fe;hpb=d43ef73bf26614af9b01fd57baa1a1fcf24bfade;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index c61baee..1683f78 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -1,14 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Keystone : Board initialization * * (C) Copyright 2014 * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ */ #include +#include #include "board.h" +#include +#include +#include +#include #include #include #include @@ -42,14 +46,14 @@ int dram_init(void) ddr3_size = ddr3_init(); - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) - if (!board_is_k2g_ice()) + if (!(board_is_k2g_ice() || board_is_k2g_i1())) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); #endif - if (!board_is_k2g_ice()) { + if (!(board_is_k2g_ice() || board_is_k2g_i1())) { if (ddr3_size) ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); else @@ -60,65 +64,16 @@ int dram_init(void) return 0; } -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -#ifndef CONFIG_DM_ETH -int get_eth_env_param(char *env_name) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { - char *env; - int res = -1; - - env = getenv(env_name); - if (env) - res = simple_strtol(env, NULL, 0); - - return res; + return (struct legacy_img_hdr *)(CONFIG_TEXT_BASE); } -int board_eth_init(bd_t *bis) +int board_init(void) { - int j; - int res; - int port_num; - char link_type_name[32]; - - if (cpu_is_k2g()) - writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); - - /* By default, select PA PLL clock as PA clock source */ -#ifndef CONFIG_SOC_K2G - if (psc_enable_module(KS2_LPSC_PA)) - return -1; -#endif - if (psc_enable_module(KS2_LPSC_CPGMAC)) - return -1; - if (psc_enable_module(KS2_LPSC_CRYPTO)) - return -1; - - if (cpu_is_k2e() || cpu_is_k2l()) - pll_pa_clk_sel(); - - port_num = get_num_eth_ports(); - - for (j = 0; j < port_num; j++) { - sprintf(link_type_name, "sgmii%d_link_type", j); - res = get_eth_env_param(link_type_name); - if (res >= 0) - eth_priv_cfg[j].sgmii_link_type = res; - - keystone2_emac_initialize(ð_priv_cfg[j]); - } - + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } -#endif -#endif #ifdef CONFIG_SPL_BUILD void spl_board_init(void) @@ -139,7 +94,7 @@ u32 spl_boot_device(void) #endif #ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) +int ft_board_setup(void *blob, struct bd_info *bd) { int lpae; char *env; @@ -147,14 +102,10 @@ int ft_board_setup(void *blob, bd_t *bd) int nbanks; u64 size[2]; u64 start[2]; - int nodeoffset; u32 ddr3a_size; - int unitrd_fixup = 0; - env = getenv("mem_lpae"); + env = env_get("mem_lpae"); lpae = env && simple_strtol(env, NULL, 0); - env = getenv("uinitrd_fixup"); - unitrd_fixup = env && simple_strtol(env, NULL, 0); ddr3a_size = 0; if (lpae) { @@ -169,8 +120,8 @@ int ft_board_setup(void *blob, bd_t *bd) /* adjust memory start address for LPAE */ if (lpae) { - start[0] -= CONFIG_SYS_SDRAM_BASE; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + start[0] -= CFG_SYS_SDRAM_BASE; + start[0] += CFG_SYS_LPAE_SDRAM_BASE; } if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { @@ -180,38 +131,55 @@ int ft_board_setup(void *blob, bd_t *bd) } /* reserve memory at start of bank */ - env = getenv("mem_reserve_head"); + env = env_get("mem_reserve_head"); if (env) { start[0] += ustrtoul(env, &endp, 0); size[0] -= ustrtoul(env, &endp, 0); } - env = getenv("mem_reserve"); + env = env_get("mem_reserve"); if (env) size[0] -= ustrtoul(env, &endp, 0); fdt_fixup_memory_banks(blob, start, size, nbanks); + return 0; +} + +void ft_board_setup_ex(void *blob, struct bd_info *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + int unitrd_fixup = 0; + + env = env_get("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = env_get("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + /* Fix up the initrd */ if (lpae && unitrd_fixup) { + int nodeoffset; int err; - u32 *prop1, *prop2; + u64 *prop1, *prop2; u64 initrd_start, initrd_end; nodeoffset = fdt_path_offset(blob, "/chosen"); if (nodeoffset >= 0) { - prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + prop1 = (u64 *)fdt_getprop(blob, nodeoffset, "linux,initrd-start", NULL); - prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + prop2 = (u64 *)fdt_getprop(blob, nodeoffset, "linux,initrd-end", NULL); if (prop1 && prop2) { - initrd_start = __be32_to_cpu(*prop1); - initrd_start -= CONFIG_SYS_SDRAM_BASE; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __be64_to_cpu(*prop1); + initrd_start -= CFG_SYS_SDRAM_BASE; + initrd_start += CFG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); - initrd_end = __be32_to_cpu(*prop2); - initrd_end -= CONFIG_SYS_SDRAM_BASE; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __be64_to_cpu(*prop2); + initrd_end -= CFG_SYS_SDRAM_BASE; + initrd_end += CFG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); err = fdt_delprop(blob, nodeoffset, @@ -241,19 +209,6 @@ int ft_board_setup(void *blob, bd_t *bd) } } - return 0; -} - -void ft_board_setup_ex(void *blob, bd_t *bd) -{ - int lpae; - u64 size; - char *env; - u64 *reserve_start; - - env = getenv("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - if (lpae) { /* * the initrd and other reserved memory areas are @@ -266,9 +221,9 @@ void ft_board_setup_ex(void *blob, bd_t *bd) *reserve_start = __cpu_to_be64(*reserve_start); size = __cpu_to_be64(*(reserve_start + 1)); if (size) { - *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; + CFG_SYS_LPAE_SDRAM_BASE; *reserve_start = __cpu_to_be64(*reserve_start); } else {