X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fsunxi%2Fboard.c;h=800f412b383ddf9ac90972e50a684c534d40fea4;hb=235c5b8315c6a9eb566fd3d99a098cc6db869fc5;hp=5e48756392f17de8d18cb7cc65c6c9ab71ecc5bc;hpb=f221961e963fcfa5ceab6455c24d6532877ca923;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 5e48756..800f412 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -20,16 +20,20 @@ #include #include #include +#include #include #ifndef CONFIG_ARM64 #include #endif #include #include +#include +#include #include #include #include #include +#include #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ @@ -74,10 +78,104 @@ static int soft_i2c_board_init(void) { return 0; } DECLARE_GLOBAL_DATA_PTR; +void i2c_init_board(void) +{ +#ifdef CONFIG_I2C0_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); + clock_twi_onoff(0, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); + clock_twi_onoff(0, 1); +#endif +#endif + +#ifdef CONFIG_I2C1_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); + clock_twi_onoff(1, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); + sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); + clock_twi_onoff(1, 1); +#endif +#endif + +#ifdef CONFIG_I2C2_ENABLE +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); + clock_twi_onoff(2, 1); +#elif defined(CONFIG_MACH_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); + sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); + clock_twi_onoff(2, 1); +#endif +#endif + +#ifdef CONFIG_I2C3_ENABLE +#if defined(CONFIG_MACH_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); + clock_twi_onoff(3, 1); +#elif defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); + sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); + clock_twi_onoff(3, 1); +#endif +#endif + +#ifdef CONFIG_I2C4_ENABLE +#if defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) + sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); + sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); + clock_twi_onoff(4, 1); +#endif +#endif + +#ifdef CONFIG_R_I2C_ENABLE + clock_twi_onoff(5, 1); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); +#endif +} + /* add board specific code here */ int board_init(void) { - __maybe_unused int id_pfr1, ret; + __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); @@ -97,14 +195,14 @@ int board_init(void) * we avoid the risk of writing to it. */ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); - if (freq != CONFIG_TIMER_CLK_FREQ) { + if (freq != COUNTER_FREQUENCY) { debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", - freq, CONFIG_TIMER_CLK_FREQ); + freq, COUNTER_FREQUENCY); #ifdef CONFIG_NON_SECURE printf("arch timer frequency is wrong, but cannot adjust it\n"); #else asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_TIMER_CLK_FREQ)); + : : "r"(COUNTER_FREQUENCY)); #endif } } @@ -115,12 +213,22 @@ int board_init(void) return ret; #ifdef CONFIG_SATAPWR - gpio_request(CONFIG_SATAPWR, "satapwr"); - gpio_direction_output(CONFIG_SATAPWR, 1); + satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); + gpio_request(satapwr_pin, "satapwr"); + gpio_direction_output(satapwr_pin, 1); #endif #ifdef CONFIG_MACPWR - gpio_request(CONFIG_MACPWR, "macpwr"); - gpio_direction_output(CONFIG_MACPWR, 1); + macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); + gpio_request(macpwr_pin, "macpwr"); + gpio_direction_output(macpwr_pin, 1); +#endif + +#ifdef CONFIG_DM_I2C + /* + * Temporary workaround for enabling I2C clocks until proper sunxi DM + * clk, reset and pinctrl drivers land. + */ + i2c_init_board(); #endif /* Uses dm gpio code so do this here and not in i2c_init_board() */ @@ -134,7 +242,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_SUNXI) static void nand_pinmux_setup(void) { unsigned int pin; @@ -171,10 +279,13 @@ void board_nand_init(void) { nand_pinmux_setup(); nand_clock_setup(); +#ifndef CONFIG_SPL_BUILD + sunxi_nand_init(); +#endif } #endif -#ifdef CONFIG_GENERIC_MMC +#ifdef CONFIG_MMC static void mmc_pinmux_setup(int sdc) { unsigned int pin; @@ -193,7 +304,8 @@ static void mmc_pinmux_setup(int sdc) case 1: pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) if (pins == SUNXI_GPIO_H) { /* SDC1: PH22-PH-27 */ for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { @@ -288,6 +400,17 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } +#elif defined(CONFIG_MACH_SUN8I_R40) + /* SDC2: PC6-PC15, PC24 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + + sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(SUNXI_GPC(24), 2); #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { @@ -301,13 +424,21 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(pin, 2); } +#elif defined(CONFIG_MACH_SUN9I) + /* SDC2: PC6-PC16 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } #endif break; case 3: pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) +#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_R40) /* SDC3: PI4-PI9 */ for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); @@ -367,8 +498,7 @@ int board_mmc_init(bd_t *bis) * are searched there first. Note we only do this for u-boot proper, * not for the SPL, see spl_boot_device(). */ - if (!sunxi_mmc_has_egon_boot_signature(mmc0) && - sunxi_mmc_has_egon_boot_signature(mmc1)) { + if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { /* Booting from emmc / mmc2, swap */ mmc0->block_dev.devnum = 1; mmc1->block_dev.devnum = 0; @@ -379,96 +509,10 @@ int board_mmc_init(bd_t *bis) } #endif -void i2c_init_board(void) -{ -#ifdef CONFIG_I2C0_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); - clock_twi_onoff(0, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); - sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); - clock_twi_onoff(0, 1); -#endif -#endif - -#ifdef CONFIG_I2C1_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); - clock_twi_onoff(1, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); - sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); - clock_twi_onoff(1, 1); -#endif -#endif - -#ifdef CONFIG_I2C2_ENABLE -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN5I) - sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); - clock_twi_onoff(2, 1); -#elif defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); - sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); - clock_twi_onoff(2, 1); -#endif -#endif - -#ifdef CONFIG_I2C3_ENABLE -#if defined(CONFIG_MACH_SUN6I) - sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); - sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); - clock_twi_onoff(3, 1); -#elif defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); - sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); - clock_twi_onoff(3, 1); -#endif -#endif - -#ifdef CONFIG_I2C4_ENABLE -#if defined(CONFIG_MACH_SUN7I) - sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); - sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); - clock_twi_onoff(4, 1); -#endif -#endif - -#ifdef CONFIG_R_I2C_ENABLE - clock_twi_onoff(5, 1); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); -#endif -} - #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { int power_failed = 0; - unsigned long ramsize; #ifdef CONFIG_SY8106A_POWER power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); @@ -529,9 +573,9 @@ void sunxi_board_init(void) #endif #endif printf("DRAM:"); - ramsize = sunxi_dram_init(); - printf(" %d MiB\n", (int)(ramsize >> 20)); - if (!ramsize) + gd->ram_size = sunxi_dram_init(); + printf(" %d MiB\n", (int)(gd->ram_size >> 20)); + if (!gd->ram_size) hang(); /* @@ -572,10 +616,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -#if !defined(CONFIG_SPL_BUILD) -#include -#include - /* * Check the SPL header for the "sunxi" variant. If found: parse values * that might have been passed by the loader ("fel" utility), and update @@ -601,14 +641,13 @@ static void parse_spl_header(const uint32_t spl_addr) * data is expected in uEnv.txt compatible format, so "env * import -t" the string(s) at fel_script_address right away. */ - himport_r(&env_htab, (char *)spl->fel_script_address, + himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); return; } /* otherwise assume .scr format (mkimage-type script) */ setenv_hex("fel_scriptaddr", spl->fel_script_address); } -#endif /* * Note this function gets called multiple times. @@ -623,7 +662,28 @@ static void setup_environment(const void *fdt) int i, ret; ret = sunxi_get_sid(sid); - if (ret == 0 && sid[0] != 0 && sid[3] != 0) { + if (ret == 0 && sid[0] != 0) { + /* + * The single words 1 - 3 of the SID have quite a few bits + * which are the same on many models, so we take a crc32 + * of all 3 words, to get a more unique value. + * + * Note we only do this on newer SoCs as we cannot change + * the algorithm on older SoCs since those have been using + * fixed mac-addresses based on only using word 3 for a + * long time and changing a fixed mac-address with an + * u-boot update is not good. + */ +#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ + !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ + !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) + sid[3] = crc32(0, (unsigned char *)&sid[1], 12); +#endif + + /* Ensure the NIC specific bytes of the mac are not all 0 */ + if ((sid[3] & 0xffffff) == 0) + sid[3] |= 0x800000; + for (i = 0; i < 4; i++) { sprintf(ethaddr, "ethernet%d", i); if (!fdt_get_alias(fdt, ethaddr)) @@ -657,12 +717,10 @@ static void setup_environment(const void *fdt) } } -#ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { __maybe_unused int ret; -#if !defined(CONFIG_SPL_BUILD) setenv("fel_booted", NULL); setenv("fel_scriptaddr", NULL); /* determine if we are running in FEL mode */ @@ -670,7 +728,6 @@ int misc_init_r(void) setenv("fel_booted", "1"); parse_spl_header(SPL_ADDR); } -#endif setup_environment(gd->fdt_blob); @@ -683,7 +740,6 @@ int misc_init_r(void) return 0; } -#endif int ft_board_setup(void *blob, bd_t *bd) { @@ -702,3 +758,32 @@ int ft_board_setup(void *blob, bd_t *bd) #endif return 0; } + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; + const char *cmp_str = (void *)(ulong)SPL_ADDR; + + /* Check if there is a DT name stored in the SPL header and use that. */ + if (spl->dt_name_offset) { + cmp_str += spl->dt_name_offset; + } else { +#ifdef CONFIG_DEFAULT_DEVICE_TREE + cmp_str = CONFIG_DEFAULT_DEVICE_TREE; +#else + return 0; +#endif + }; + +/* Differentiate the two Pine64 board DTs by their DRAM size. */ + if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { + if ((gd->ram_size > 512 * 1024 * 1024)) + return !strstr(name, "plus"); + else + return !!strstr(name, "plus"); + } else { + return strcmp(name, cmp_str); + } +} +#endif