X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fsiemens%2Fdxr2%2Fboard.c;h=217237900e36bd47baa46a400fed8862f168176f;hb=cc07294bc704694ae33db75b25ac557e5917a83f;hp=af9d84f12828105d036863cff0e3f440161f836a;hpb=89993dc34afeeca4dad84e3c2db7403c406ccb78;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f..2172379 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -38,11 +38,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
+/* @303MHz-i0 */
 const struct ddr3_data ddr3_default = {
-	0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
-	0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
-	0x00000618,
+	0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
+	0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+	0x00000618, 0x0000014A,
 };
 
 static void set_default_ddr3_timings(void)
@@ -73,6 +73,7 @@ static void print_ddr3_timings(void)
 
 	PRINTARGS(sdram_config);
 	PRINTARGS(ref_ctrl);
+	PRINTARGS(ioctr_val);
 }
 
 static void print_chip_data(void)
@@ -139,14 +140,14 @@ struct emif_regs dxr2_ddr3_emif_reg_data = {
 };
 
 struct ddr_data dxr2_ddr3_data = {
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
-	.cmd0dldiff = 0,
-	.cmd1dldiff = 0,
-	.cmd2dldiff = 0,
 };
+
+struct ctrl_ioregs dxr2_ddr3_ioregs = {
+};
+
 	/* pass values from eeprom */
 	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 	dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
@@ -168,7 +169,13 @@ struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+	dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
+	dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
+
+	config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
 		   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 
@@ -191,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
+		.phy_addr	= 0,
 		.phy_if		= PHY_INTERFACE_MODE_MII,
 	},
 };
@@ -225,6 +232,13 @@ int board_eth_init(bd_t *bis)
 
 	factoryset_setenv();
 
+	/* Reset SMSC LAN9303 switch for default configuration */
+	gpio_request(GPIO_LAN9303_NRST, "nRST");
+	gpio_direction_output(GPIO_LAN9303_NRST, 0);
+	/* assert active low reset for 200us */
+	udelay(200);
+	gpio_set_value(GPIO_LAN9303_NRST, 1);
+
 	/* Set rgmii mode and enable rmii clock to be sourced from chip */
 	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);