X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fsamsung%2Forigen%2Flowlevel_init.S;h=be9d418265c2fda2f64928edeb542fb3d1950003;hb=d72da1582895ca226b995758426ec3769b54a9b8;hp=928320120160a63fc1e18e7cdf0888ad000a1e48;hpb=e390e8709149664ff96cf19384264c84573f3082;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 9283201..be9d418 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -87,12 +87,14 @@ lowlevel_init:
 1:
 	/* for UART */
 	bl uart_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 	pop	{pc}
 
 wakeup_reset:
 	bl system_clock_init
 	bl mem_ctrl_asm_init
+	bl arch_cpu_init
 	bl tzpc_init
 
 exit_wakeup:
@@ -158,7 +160,22 @@ system_clock_init:
 	ldr	r2, =CLK_SRC_PERIL0_OFFSET
 	str	r1, [r0, r2]
 
-	/* FIMD0 */
+	/* CAM , FIMC 0-3 */
+	ldr	r1, =CLK_SRC_CAM_VAL
+	ldr	r2, =CLK_SRC_CAM_OFFSET
+	str	r1, [r0, r2]
+
+	/* MFC */
+	ldr	r1, =CLK_SRC_MFC_VAL
+	ldr	r2, =CLK_SRC_MFC_OFFSET
+	str	r1, [r0, r2]
+
+	/* G3D */
+	ldr	r1, =CLK_SRC_G3D_VAL
+	ldr	r2, =CLK_SRC_G3D_OFFSET
+	str	r1, [r0, r2]
+
+	/* LCD0 */
 	ldr	r1, =CLK_SRC_LCD0_VAL
 	ldr	r2, =CLK_SRC_LCD0_OFFSET
 	str	r1, [r0, r2]
@@ -223,6 +240,26 @@ system_clock_init:
 	ldr	r2, =CLK_DIV_PERIL0_OFFSET
 	str	r1, [r0, r2]
 
+	/* CAM, FIMC 0-3: CAM Clock Divisors */
+	ldr	r1, =CLK_DIV_CAM_VAL
+	ldr	r2, =CLK_DIV_CAM_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_MFC: MFC Clock Divisors */
+	ldr	r1, =CLK_DIV_MFC_VAL
+	ldr	r2, =CLK_DIV_MFC_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_G3D: G3D Clock Divisors */
+	ldr	r1, =CLK_DIV_G3D_VAL
+	ldr	r2, =CLK_DIV_G3D_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_LCD0: LCD0 Clock Divisors */
+	ldr	r1, =CLK_DIV_LCD0_VAL
+	ldr	r2, =CLK_DIV_LCD0_OFFSET
+	str	r1, [r0, r2]
+
 	/* Set PLL locktime */
 	ldr	r1, =PLL_LOCKTIME
 	ldr	r2, =APLL_LOCK_OFFSET
@@ -318,45 +355,3 @@ uart_asm_init:
 	nop
 	nop
 
-/* Setting TZPC[TrustZone Protection Controller] */
-tzpc_init:
-	ldr	r0, =TZPC0_BASE
-	mov	r1, #R0SIZE
-	str	r1, [r0]
-	mov	r1, #DECPROTXSET
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC1_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC2_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC3_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC4_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	ldr	r0, =TZPC5_BASE
-	str	r1, [r0, #TZPC_DECPROT0SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT1SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT2SET_OFFSET]
-	str	r1, [r0, #TZPC_DECPROT3SET_OFFSET]
-
-	mov	pc, lr