X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Frenesas%2Fulcb%2Fulcb.c;h=b91f940b487ecd6b94cc2d62f3419e568fc0a8fb;hb=b641dd3ec8dc3f6b18d2fa945ac3ab597063d191;hp=ed891c833c3e33fbe00731b5c2f4b7b7823e3013;hpb=76cc372879e2f2f0467e8a3875f097d189647793;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index ed891c8..b91f940 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * board/renesas/ulcb/ulcb.c
  *     This file is ULCB board support.
  *
  * Copyright (C) 2017 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
@@ -27,48 +26,22 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CPGWPCR	0xE6150904
-#define CPGWPR  0xE615090C
-
-#define CLK2MHZ(clk)	(clk / 1000 / 1000)
 void s_init(void)
 {
-	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
-	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-
-	/* Watchdog init */
-	writel(0xA5A5A500, &rwdt->rwtcsra);
-	writel(0xA5A5A500, &swdt->swtcsra);
-
-	writel(0xA5A50000, CPGWPCR);
-	writel(0xFFFFFFFF, CPGWPR);
 }
 
-#define GSX_MSTP112		BIT(12)	/* 3DG */
-#define TMU0_MSTP125		BIT(25)	/* secure */
-#define TMU1_MSTP124		BIT(24)	/* non-secure */
-#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
 #define DVFS_MSTP926		BIT(26)
 #define HSUSB_MSTP704		BIT(4)	/* HSUSB */
 
 int board_early_init_f(void)
 {
-	/* TMU0,1 */		/* which use ? */
-	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
 	/* DVFS for reset */
-	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+	mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
 	return 0;
 }
 
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define	SYSC_PWRSR2	0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define	SYSC_PWRONCR2	0xE618010C
-
 /* HSUSB block registers */
 #define HSUSB_REG_LPSTS			0xE6590102
 #define HSUSB_REG_LPSTS_SUSPM_NORMAL	BIT(14)
@@ -85,7 +58,7 @@ int board_init(void)
 	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
 	/* Configure the HSUSB block */
-	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+	mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
 	/* Choice USB0SEL */
 	clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
 			HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
@@ -95,17 +68,24 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
+#ifdef CONFIG_MULTI_DTB_FIT
+int board_fit_config_name_match(const char *name)
 {
-	if (fdtdec_setup_memory_size() != 0)
-		return -EINVAL;
+	/* PRR driver is not available yet */
+	u32 cpu_type = rmobile_get_cpu_type();
 
-	return 0;
-}
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
+	    !strcmp(name, "r8a77950-ulcb-u-boot"))
+		return 0;
 
-int dram_init_banksize(void)
-{
-	fdtdec_setup_memory_banksize();
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
+	    !strcmp(name, "r8a77960-ulcb-u-boot"))
+		return 0;
 
-	return 0;
+	if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
+	    !strcmp(name, "r8a77965-ulcb-u-boot"))
+		return 0;
+
+	return -1;
 }
+#endif