X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Frenesas%2Fporter%2Fporter.c;h=db1fb4b035f000bb6a46dee10b42f3b6d65da469;hb=aa6e94deabb45154cea07ad44c4a5c047bca078b;hp=86dea8bfa7a3bf85c437bffde313df9faa3de3f2;hpb=1a7f6d4597646662022f3e67ceaaeff7a23459e5;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 86dea8b..db1fb4b 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -1,19 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 /* * board/renesas/porter/porter.c * * Copyright (C) 2015 Renesas Electronics Corporation * Copyright (C) 2015 Cogent Embedded, Inc. - * - * SPDX-License-Identifier: GPL-2.0 */ #include +#include +#include +#include +#include +#include #include #include +#include #include +#include #include #include #include +#include +#include #include #include #include @@ -40,7 +48,7 @@ void s_init(void) writel(0xA5A5A500, &swdt->swtcsra); /* CPU frequency setting. Set to 1.5GHz */ - stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; + stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT; clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); /* QoS */ @@ -65,17 +73,25 @@ int board_early_init_f(void) return 0; } +#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ + int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } int dram_init(void) { - if (fdtdec_setup_memory_size() != 0) + if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; return 0; @@ -90,7 +106,7 @@ int dram_init_banksize(void) /* porter has KSZ8041RNLI */ #define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE 0xC000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { @@ -102,16 +118,40 @@ int board_phy_config(struct phy_device *phydev) return 0; } -const struct rmobile_sysinfo sysinfo = { - CONFIG_ARCH_RMOBILE_BOARD_STRING -}; +void reset_cpu(void) +{ + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x5a; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); -void reset_cpu(ulong addr) + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); +} + +enum env_location env_get_location(enum env_operation op, int prio) { - u8 val; + const u32 load_magic = 0xb33fc0de; + + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; - i2c_set_bus_num(2); /* PowerIC connected to ch2 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + return ENVL_SPI_FLASH; }