X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Frenesas%2Falt%2Falt.c;h=7598b1a4b92b698827e790cef44e85b517b8f970;hb=bb6d2ff2ac96a6b3d83f7f65483a2f8087d1f902;hp=b668bf6e9714f324c0b2861036407e1a1a78b2d1;hpb=ca7bc8ff0d5255a85edf5d451d5e68006044e7cc;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index b668bf6..7598b1a 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -1,20 +1,26 @@
 /*
  * board/renesas/alt/alt.c
  *
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014, 2015 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <common.h>
 #include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
@@ -37,136 +43,107 @@ void s_init(void)
 	qos_init();
 }
 
-#define MSTPSR1		0xE6150038
-#define SMSTPCR1	0xE6150134
-#define TMU0_MSTP125	(1 << 25)
+#define TMU0_MSTP125	BIT(25)
+#define MMC0_MSTP315	BIT(15)
 
-#define MSTPSR7		0xE61501C4
-#define SMSTPCR7	0xE615014C
-#define SCIF0_MSTP719	(1 << 19)
-
-#define MSTPSR8		0xE61509A0
-#define SMSTPCR8	0xE6150990
-#define ETHER_MSTP813	(1 << 13)
-
-#define mstp_setbits(type, addr, saddr, set) \
-	out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-	out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
-	mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear)   \
-	mstp_clrbits(le32, addr, saddr, clear)
+#define SD1CKCR		0xE6150078
+#define SD_97500KHZ	0x7
 
 int board_early_init_f(void)
 {
 	/* TMU */
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 
-	/* SCIF0 */
-	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
-
-	/* ETHER */
-	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+	/* Set SD1 to the 97.5MHz */
+	writel(SD_97500KHZ, SD1CKCR);
 
 	return 0;
 }
 
-void arch_preboot_os(void)
-{
-	/* Disable TMU0 */
-	mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-}
+#define ETHERNET_PHY_RESET	56	/* GPIO 1 24 */
 
 int board_init(void)
 {
 	/* adress of boot parameters */
-	gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
-
-	/* Init PFC controller */
-	r8a7794_pinmux_init();
-
-	/* Ether Enable */
-	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
-	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
-	gpio_request(GPIO_FN_ETH_RXD0, NULL);
-	gpio_request(GPIO_FN_ETH_RXD1, NULL);
-	gpio_request(GPIO_FN_ETH_LINK, NULL);
-	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
-	gpio_request(GPIO_FN_ETH_MDIO, NULL);
-	gpio_request(GPIO_FN_ETH_TXD1, NULL);
-	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
-	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
-	gpio_request(GPIO_FN_ETH_TXD0, NULL);
-	gpio_request(GPIO_FN_ETH_MDC, NULL);
-	gpio_request(GPIO_FN_IRQ8, NULL);
-
-	/* PHY reset */
-	gpio_request(GPIO_GP_1_24, NULL);
-	gpio_direction_output(GPIO_GP_1_24, 0);
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Force ethernet PHY out of reset */
+	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
+	gpio_direction_output(ETHERNET_PHY_RESET, 0);
 	mdelay(20);
-	gpio_set_value(GPIO_GP_1_24, 1);
+	gpio_direction_output(ETHERNET_PHY_RESET, 1);
 	udelay(1);
 
 	return 0;
 }
 
-#define CXR24 0xEE7003C0 /* MAC address high register */
-#define CXR25 0xEE7003C8 /* MAC address low register */
-int board_eth_init(bd_t *bis)
+int dram_init(void)
 {
-#ifdef CONFIG_SH_ETHER
-	int ret = -ENODEV;
-	u32 val;
-	unsigned char enetaddr[6];
-
-	ret = sh_eth_initialize(bis);
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		return ret;
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
-	/* Set Mac address */
-	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
-		enetaddr[2] << 8 | enetaddr[3];
-	writel(val, CXR24);
+	return 0;
+}
 
-	val = enetaddr[4] << 8 | enetaddr[5];
-	writel(val, CXR25);
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
 
-	return ret;
-#else
 	return 0;
-#endif
 }
 
-int dram_init(void)
+/* KSZ8041RNLI */
+#define PHY_CONTROL1		0x1E
+#define PHY_LED_MODE		0xC0000
+#define PHY_LED_MODE_ACK	0x4000
+int board_phy_config(struct phy_device *phydev)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+	ret &= ~PHY_LED_MODE;
+	ret |= PHY_LED_MODE_ACK;
+	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
 
 	return 0;
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
-void dram_init_banksize(void)
+void reset_cpu(ulong addr)
 {
-	gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
-}
+	struct udevice *dev;
+	const u8 pmic_bus = 1;
+	const u8 pmic_addr = 0x58;
+	u8 data;
+	int ret;
 
-int board_late_init(void)
-{
-	return 0;
+	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
+	if (ret)
+		hang();
+
+	ret = dm_i2c_read(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
+
+	data |= BIT(1);
+
+	ret = dm_i2c_write(dev, 0x13, &data, 1);
+	if (ret)
+		hang();
 }
 
-void reset_cpu(ulong addr)
+enum env_location env_get_location(enum env_operation op, int prio)
 {
-	u8 val;
+	const u32 load_magic = 0xb33fc0de;
+
+	/* Block environment access if loaded using JTAG */
+	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
+	    (op != ENVOP_INIT))
+		return ENVL_UNKNOWN;
+
+	if (prio)
+		return ENVL_UNKNOWN;
 
-	i2c_set_bus_num(1); /* PowerIC connected to ch3 */
-	i2c_init(400000, 0);
-	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
-	val |= 0x02;
-	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+	return ENVL_SPI_FLASH;
 }