X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fprodrive%2Falpr%2Falpr.c;h=be79b42bd041701309faf3be7a7f4f90099dcfe5;hb=297a65873d2cb2bd296253af51f59cc1391afbff;hp=287f32e587a0ec398d3280fbfdbf04e0d3f97a23;hpb=34e6cb8d1d9dc8194b2d8cad1cc39273ac58f8d8;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 287f32e..be79b42 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -39,7 +39,7 @@ int board_early_init_f (void) /*------------------------------------------------------------------------- * Initialize EBC CONFIG *-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -48,43 +48,55 @@ int board_early_init_f (void) /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe03); /* per manual */ - mtdcr (uic0tr, 0x01c00000); /* per manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - + /* + * Because of the interrupt handling rework to handle 440GX interrupts + * with the common code, we needed to change names of the UIC registers. + * Here the new relationship: + * + * U-Boot name 440GX name + * ----------------------- + * UIC0 UICB0 + * UIC1 UIC0 + * UIC2 UIC1 + * UIC3 UIC2 + */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr (uic1pr, 0xfffffe03); /* per manual */ + mtdcr (uic1tr, 0x01c00000); /* per manual */ mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr (uic2sr, 0xffffffff); /* clear all */ mtdcr (uic2er, 0x00000000); /* disable all */ mtdcr (uic2cr, 0x00000000); /* all non-critical */ - mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */ mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr (uic2sr, 0xffffffff); /* clear all */ - mtdcr (uicb0sr, 0xfc000000); /* clear all */ - mtdcr (uicb0er, 0x00000000); /* disable all */ - mtdcr (uicb0cr, 0x00000000); /* all non-critical */ - mtdcr (uicb0pr, 0xfc000000); /* */ - mtdcr (uicb0tr, 0x00000000); /* */ - mtdcr (uicb0vr, 0x00000001); /* */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + mtdcr (uic3er, 0x00000000); /* disable all */ + mtdcr (uic3cr, 0x00000000); /* all non-critical */ + mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ + mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ + mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic3sr, 0xffffffff); /* clear all */ + + mtdcr (uic0sr, 0xfc000000); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non-critical */ + mtdcr (uic0pr, 0xfc000000); /* */ + mtdcr (uic0tr, 0x00000000); /* */ + mtdcr (uic0vr, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); /* Setup GPIO/IRQ multiplexing */ - mtsdr(sdr_pfc0, 0x01a33e00); + mtsdr(SDR0_PFC0, 0x01a33e00); return 0; } @@ -112,8 +124,8 @@ int last_stage_init(void) static int board_rev(void) { /* Setup as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); return (in32(GPIO0_IR) >> 16) & 0x3; } @@ -132,36 +144,6 @@ int checkboard (void) return (0); } -#if defined(CFG_DRAM_TEST) -int testdram (void) -{ - uint *pstart = (uint *) 0x00000000; - uint *pend = (uint *) 0x08000000; - uint *p; - - for (p = pstart; p < pend; p++) - *p = 0xaaaaaaaa; - - for (p = pstart; p < pend; p++) { - if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - - for (p = pstart; p < pend; p++) - *p = 0x55555555; - - for (p = pstart; p < pend; p++) { - if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); - return 1; - } - } - return 0; -} -#endif - /************************************************************************* * pci_pre_init * @@ -183,7 +165,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; @@ -204,7 +186,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -219,7 +201,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -228,12 +210,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host @@ -257,11 +239,11 @@ static void wait_for_pci_ready(void) /* * Configure EREADY as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); udelay(1000); for (;;) { - if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) return; } @@ -278,7 +260,7 @@ int is_pci_host(struct pci_controller *hose) * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -292,19 +274,19 @@ void pci_master_init(struct pci_controller *hose) out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ - out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ #ifdef CONFIG_POST /* @@ -317,24 +299,3 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[4]; - int rc; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; - rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */