X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fnetstal%2Fhcu5%2Fhcu5.c;h=c545cc01ea760fb64a1a32dad41e32edc7e363b0;hb=bb3bcfa2426cc6a0aecec7270e3ee67ca843a125;hp=2c7afe277e71e99cfec328c5ff15d69a8f529ae2;hpb=e57ed96baca1222e6cd3d7032691a89d5890bb4a;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 2c7afe2..c545cc0 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,11 +22,13 @@ #include #include #include +#include + #include "../common/nm.h" DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #undef BOOTSTRAP_OPTION_A_ACTIVE @@ -40,9 +42,9 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) -#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) -#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000) +#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000) +#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000) #define HCU_SW_INSTALL_REQUESTED 0x10 /* @@ -89,13 +91,13 @@ int board_early_init_f(void) /* * Initiate system reset in debug control register DBCR */ - dbcr = mfspr(dbcr0); - mtspr(dbcr0, dbcr | CHIP_RESET); + dbcr = mfspr(SPRN_DBCR0); + mtspr(SPRN_DBCR0, dbcr | CHIP_RESET); } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -129,31 +131,31 @@ int board_early_init_f(void) /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ - mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ + mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350); @@ -212,7 +214,7 @@ void hcu_led_set(u32 value) */ u32 get_serial_number(void) { - u32 *serial = (u32 *)CFG_FLASH_BASE; + u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE; if (in_be32(serial) == 0xffffffff) return 0; @@ -240,18 +242,18 @@ int misc_init_r(void) unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif #endif @@ -307,17 +309,15 @@ int misc_init_r(void) /* We cannot easily enable trace before, as there are other * routines messing around with sdr0_pfc1. And I do not need it. */ - if (mfspr(dbcr0) & 0x80000000) { + if (mfspr(SPRN_DBCR0) & 0x80000000) { /* External debugger alive - * enable trace facilty for Lauterback - * CCR0[DAPUIB]=0 Enable broadcast of instruction data - * to auxiliary processor interface - * CCR0[DTB]=0 Enable broadcast of trace information - * SDR0_PFC0[TRE] Trace signals are enabled instead of + * enable trace facilty for Lauterbach + * CCR0[DTB]=0 Enable broadcast of trace information + * SDR0_PFC0[TRE] Trace signals are enabled instead of * GPIO49-63 */ - mtspr(ccr0, mfspr(ccr0) &~ 0x00108000); - mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100); + mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB)); + mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE); } return 0; } @@ -326,7 +326,7 @@ int board_with_pci(void) { u32 reg; - mfsdr(sdr_pci0, reg); + mfsdr(SDR0_PCI0, reg); return (reg & SDR0_XCR_PAE_MASK); } @@ -352,148 +352,44 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); /* Sequoia */ + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ - mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ - mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); } /* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - */ -void pci_target_init(struct pci_controller *hose) -{ - if (!board_with_pci()) { return; } - /* - * Set up Direct MMIO registers - * - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address - * 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0MA, 0x00000000); - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIX0_PMM0MA, 0xE0000001); - - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1MA, 0x00000000); - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIX0_PMM1MA, 0xE0000001); - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); -} - -/* - * pci_master_init - * + * Override weak default pci_master_init() */ void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; - if (!board_with_pci()) { return; } - - /*--------------------------------------------------------------- - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - *--------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} + if (!board_with_pci()) + return; -/* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - * - */ -int is_pci_host(struct pci_controller *hose) -{ - return 1; + __pci_master_init(hose); } #endif /* defined(CONFIG_PCI) */ -#if defined(CONFIG_POST) -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif /* CONFIG_POST */ - #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { @@ -501,3 +397,18 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +}