X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fms7750se%2Flowlevel_init.S;h=9cd2705e5def8f3cca349aa123fbc7fd6a99c82e;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=710801978293117b786d220638f08dbe0b8ad6fe;hpb=f7e78f3b74aae9caca2997bad865a72338326c0a;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
index 7108019..9cd2705 100644
--- a/board/ms7750se/lowlevel_init.S
+++ b/board/ms7750se/lowlevel_init.S
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  modified from SH-IPL+g
  Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
@@ -5,28 +6,9 @@
  Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
 
  Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
-
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
 */
 
 #include <config.h>
-#include <version.h>
 
 #include <asm/processor.h>
 #include <asm/macro.h>
@@ -84,7 +66,7 @@ init_bsc:
 	write32	MCR_A, MCR_D1
 
 	/* Set SDRAM mode */
-	write8	SDMR3_A, #0
+	write8	SDMR3_A, SDMR3_D
 
 	! Do you need PCMCIA setting?
 	! If so, please add the lines here...
@@ -108,7 +90,7 @@ init_bsc:
 	write32	MCR_A, MCR_D2
 
 	/* Set SDRAM mode */
-	write8	SDMR3_A, #0
+	write8	SDMR3_A, SDMR3_D
 
 	rts
 	nop
@@ -120,13 +102,14 @@ CCR_D_DISABLE:	.long	0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
 #ifdef CONFIG_CPU_TYPE_R
-		.long	0x00000e1a	/* 12:3:3 */
+		.word	0x0e1a	/* 12:3:3 */
 #else	/* CONFIG_CPU_TYPE_R */
 #ifdef CONFIG_GOOD_SESH4
-		.long	0x00000e13	/* 6:2:1 */
+		.word	0x00e13	/* 6:2:1 */
 #else
-		.long	0x00000e23	/* 6:1:1 */
+		.word	0x00e23	/* 6:1:1 */
 #endif
+.align 2
 #endif	/* CONFIG_CPU_TYPE_R */
 
 BCR1_A:		.long	BCR1
@@ -140,14 +123,19 @@ WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
 WCR3_A:		.long	WCR3
 WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
 RTCSR_A:	.long	RTCSR
-RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
+RTCSR_D:	.word	0xA518		/* RTCSR Write Code A5h Data 18h */
+.align 2
 RTCNT_A:	.long	RTCNT
-RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
+RTCNT_D:	.word	0xA500		/* RTCNT Write Code A5h Data 00h */
+.align 2
 RTCOR_A:	.long	RTCOR
-RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+RTCOR_D:	.word	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
+.align 2
 SDMR3_A:	.long	SDMR3_ADDRESS
+SDMR3_D:	.long	0x00
 MCR_A:		.long	MCR
 MCR_D1:		.long	MCR_D1_VALUE
 MCR_D2:		.long	MCR_D2_VALUE
 RFCR_A:		.long	RFCR
-RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
+RFCR_D:		.word	0xA400		/* RFCR Write Code A4h Data 00h */
+.align 2