X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fmpl%2Fpip405%2Fpip405.c;h=e00d1d08f5cf59d9b6e7df64d9c1d8e853148c5e;hb=d1c3b27525b664e8c4db6bb173eed51bfc8220de;hp=a398362f96aef4fad6eab5f3f77e22681ba831f0;hpb=77ddac9480d63a80b6bb76d7ee4dcc2d1070867e;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index a398362..e00d1d0 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -28,9 +28,12 @@ #include "pip405.h" #include #include +#include #include "../common/isa.h" #include "../common/common_util.h" +DECLARE_GLOBAL_DATA_PTR; + #undef SDRAM_DEBUG #define FALSE 0 @@ -134,8 +137,6 @@ unsigned short NSto10PS (unsigned char spd_byte) void SDRAM_err (const char *s) { #ifndef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; - (void) get_clocks (); gd->baudrate = 9600; serial_init (); @@ -191,14 +192,11 @@ int board_early_init_f (void) trc_clocks, tctp_clocks; unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; -#ifdef SDRAM_DEBUG - DECLARE_GLOBAL_DATA_PTR; -#endif /* set up the config port */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, CONFIG_PORT_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, CONFIG_PORT_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); memclk = get_bus_freq (tmemclk); tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ @@ -211,7 +209,7 @@ int board_early_init_f (void) #endif /* Read Serial Presence Detect Information */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); dataout[0] = 0; for (i = 0; i < 128; i++) datain[i] = 127; @@ -255,7 +253,7 @@ int board_early_init_f (void) (datain[2] != 0x04) || /* if not SDRAM */ (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ - (datain[126] == 0x66)) /* or a 66Mhz modules */ + (datain[126] == 0x66)) /* or a 66MHz modules */ SDRAM_err ("unsupported SDRAM"); #ifdef SDRAM_DEBUG serial_puts ("SDRAM sanity ok\n"); @@ -363,8 +361,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - tmp = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ tmp |= ((unsigned long) cal_val) << 23; @@ -387,9 +385,9 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, tmp); - baseaddr = CFG_SDRAM_BASE; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, tmp); + baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; /* insert AM value */ tmp = ((unsigned long) t->mode - 1) << 13; @@ -420,8 +418,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG serial_puts ("bank0: baseaddr: "); @@ -436,12 +434,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; #ifdef SDRAM_DEBUG @@ -461,12 +459,12 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -484,12 +482,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG serial_puts ("bank3: baseaddr: "); @@ -511,13 +509,13 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) tmp |= 0x05F00000; @@ -525,14 +523,14 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); /*-------------------------------------------------------------------------+ @@ -611,10 +609,8 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -long int initdram (int board_type) +phys_size_t initdram (int board_type) { - DECLARE_GLOBAL_DATA_PTR; - unsigned long bank_reg[4], tmp, bank_size; int i, ds; unsigned long TotalSize; @@ -623,14 +619,14 @@ long int initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -666,15 +662,14 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { - DECLARE_GLOBAL_DATA_PTR; /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; gd->bd->bi_flashoffset=0; /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) + mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); } @@ -711,7 +706,7 @@ int last_stage_init (void) { print_pip405_rev (); isa_init (); - show_stdio_dev (); + stdio_print_current_devices (); check_env(); return 0; }