X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fmpl%2Fmip405%2Fmip405.c;h=b87df01fec2648a4a65de7225254d6a421f66787;hb=952e7760bfc5b0e3b142b9ce34e7fbb7d008c900;hp=34f328999d1d27b7ac8df257a791e3cd3be20964;hpb=b86d7622b33892b1dafe761a7a9eaeeab9f3816b;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 34f3289..b87df01 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -65,17 +65,15 @@ #include #include "mip405.h" #include -#include <405gp_i2c.h> +#include <4xx_i2c.h> #include #include "../common/common_util.h" +#include #include #include DECLARE_GLOBAL_DATA_PTR; -extern block_dev_desc_t * scsi_get_dev(int dev); -extern block_dev_desc_t * ide_get_dev(int dev); - #undef SDRAM_DEBUG #define ENABLE_ECC /* for ecc boards */ #define FALSE 0 @@ -92,12 +90,12 @@ extern ldiv_t ldiv (long int __numer, long int __denom); #endif -#define PLD_PART_REG PER_PLD_ADDR + 0 -#define PLD_VERS_REG PER_PLD_ADDR + 1 -#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 -#define PLD_IRQ_REG PER_PLD_ADDR + 3 -#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 -#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 +#define PLD_PART_REG PER_PLD_ADDR + 0 +#define PLD_VERS_REG PER_PLD_ADDR + 1 +#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 +#define PLD_IRQ_REG PER_PLD_ADDR + 3 +#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 +#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 #define MEGA_BYTE (1024*1024) @@ -253,21 +251,21 @@ int init_sdram (void) unsigned char bc; unsigned long sdram_tim, sdram_bank; - /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/ + /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ (void) get_clocks (); gd->baudrate = 9600; serial_init (); /* set up the pld */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, PLD_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, PLD_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, PLD_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, PLD_CR); /* THIS IS OBSOLETE */ /* set up the board rev reg*/ - mtdcr (ebccfga, pb5ap); - mtdcr (ebccfgd, BOARD_AP); - mtdcr (ebccfga, pb5cr); - mtdcr (ebccfgd, BOARD_CR); + mtdcr (EBC0_CFGADDR, PB5AP); + mtdcr (EBC0_CFGDATA, BOARD_AP); + mtdcr (EBC0_CFGADDR, PB5CR); + mtdcr (EBC0_CFGDATA, BOARD_CR); #ifdef SDRAM_DEBUG /* get all informations from PLD */ serial_puts ("\nPLD Part 0x"); @@ -291,30 +289,30 @@ int init_sdram (void) SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); #endif /* set-up the chipselect machine */ - mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ - tmp = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ + tmp = mfdcr (EBC0_CFGDATA); if ((tmp & 0x00002000) == 0) { /* MPS Boot, set up the flash */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, FLASH_CR); } else { /* Flash boot, set up the MPS */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, MPS_CR); } /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (ebccfga, pb2ap); - mtdcr (ebccfgd, UART0_AP); - mtdcr (ebccfga, pb2cr); - mtdcr (ebccfgd, UART0_CR); - mtdcr (ebccfga, pb3ap); - mtdcr (ebccfgd, UART1_AP); - mtdcr (ebccfga, pb3cr); - mtdcr (ebccfgd, UART1_CR); + mtdcr (EBC0_CFGADDR, PB2AP); + mtdcr (EBC0_CFGDATA, UART0_AP); + mtdcr (EBC0_CFGADDR, PB2CR); + mtdcr (EBC0_CFGDATA, UART0_CR); + mtdcr (EBC0_CFGADDR, PB3AP); + mtdcr (EBC0_CFGDATA, UART1_AP); + mtdcr (EBC0_CFGADDR, PB3CR); + mtdcr (EBC0_CFGDATA, UART1_CR); bc = in8 (PLD_BOARD_CFG_REG); #ifdef SDRAM_DEBUG serial_puts ("\nstart SDRAM Setup\n"); @@ -323,7 +321,7 @@ int init_sdram (void) serial_puts ("\n"); #endif i = 0; - baseaddr = CFG_SDRAM_BASE; + baseaddr = CONFIG_SYS_SDRAM_BASE; while (sdram_table[i].sz != 0xff) { if (sdram_table[i].boardtype == bc) break; @@ -350,8 +348,8 @@ int init_sdram (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ sdram_tim |= ((unsigned long) (cal_val)) << 23; /* insert PTA value */ @@ -371,8 +369,8 @@ int init_sdram (void) /* insert SZ value; */ tmp |= ((unsigned long) sdram_table[i].sz << 17); /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -382,8 +380,8 @@ int init_sdram (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, sdram_tim); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, sdram_tim); #ifdef SDRAM_DEBUG serial_puts ("mb0cf: "); @@ -392,23 +390,23 @@ int init_sdram (void) #endif /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, sdram_bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, sdram_bank); if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x07F00000; } else { /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x05F00000; } /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable ECC if used */ #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) if (sdram_table[i].ecc) { @@ -417,19 +415,19 @@ int init_sdram (void) #ifdef SDRAM_DEBUG serial_puts ("disable ECC.. "); #endif - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (memcfga, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); /* set up SDRAM Controller with ECC enabled */ #ifdef SDRAM_DEBUG serial_puts ("setup SDRAM Controller.. "); #endif - mtdcr (memcfgd, tmp); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); #ifdef SDRAM_DEBUG serial_puts ("fill the memory..\n"); @@ -449,19 +447,19 @@ int init_sdram (void) serial_puts ("enable ECC\n"); #endif udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } else #endif { /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } serial_puts ("\n"); @@ -491,13 +489,13 @@ int board_early_init_f (void) | caused the interrupt. | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ return 0; } @@ -623,7 +621,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -long int initdram (int board_type) +phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; @@ -633,14 +631,14 @@ long int initdram (int board_type) ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -650,8 +648,8 @@ long int initdram (int board_type) } else ds = 1; } - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); if (!tmp) printf ("No "); @@ -682,15 +680,15 @@ int misc_init_r (void) { /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; gd->bd->bi_flashoffset=0; /* check, if RTC is running */ rtc_get (&tm); start=get_timer(0); /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) - mtspr(ccr0, (mfspr(ccr0) & ~0x80)); + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) + mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); } @@ -738,7 +736,7 @@ int last_stage_init (void) printf ("Error writing to the PHY\n"); } print_mip405_rev (); - show_stdio_dev (); + stdio_print_current_devices (); check_env (); /* check if RTC time is valid */ stop=get_timer(start);