X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fmcc200%2Fmt48lc8m32b2-6-7.h;fp=board%2Fmcc200%2Fmt48lc8m32b2-6-7.h;h=13aebbd8af1fdebe16ccb092412370a14756b218;hb=951a954b77ef30df1f5c1b7b9b4312e783b2cbb4;hp=73dcd5c0a33f1eb901226ef41b257c102a160201;hpb=bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
index 73dcd5c..13aebbd 100644
--- a/board/mcc200/mt48lc8m32b2-6-7.h
+++ b/board/mcc200/mt48lc8m32b2-6-7.h
@@ -6,7 +6,7 @@
 
 /* Settings for XLB = 132 MHz */
 
-#define SDRAM_MODE	0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
-#define SDRAM_CONTROL	0x504f0000 // Control Register—MBAR + 0x0104
-#define SDRAM_CONFIG1	0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
-#define SDRAM_CONFIG2	0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
+#define SDRAM_MODE	0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
+#define SDRAM_CONTROL	0x504f0000 /* Control Register MBAR + 0x0104 */
+#define SDRAM_CONFIG1	0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
+#define SDRAM_CONFIG2	0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */