X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fmcc200%2Fmcc200.c;h=65b818471a817bdb6e7358383ee0dec3e97da5ee;hb=225f0eaa745adfae05931848543d99942798756a;hp=6e2d564c5bc228af47dffa9d1b8f3358855586d2;hpb=985b950a9bb1f85d3868e1ff0b1d550fb87c977c;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 6e2d564..65b8184 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,17 +27,24 @@ #include #include #include +#include /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ /* One MT48LC16M32S2 for 64 MB */ -#include "mt48lc16m32s2-75.h" +/* #include "mt48lc16m32s2-75.h" */ +#if defined (CONFIG_MCC200_SDRAM) +#include "mt48lc16m16a2-75.h" +#else +#include "mt46v16m16-75.h" +#endif DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ +extern int do_auto_update(void); ulong flash_get_size (ulong base, int banknum); #ifndef CFG_RAMBOOT @@ -85,14 +92,15 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. */ -long int initdram (int board_type) +phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -187,17 +195,39 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } int checkboard (void) { +#if defined(CONFIG_PRS200) + puts ("Board: PRS200\n"); +#else puts ("Board: MCC200\n"); +#endif return 0; } int misc_init_r (void) { + ulong flash_sup_end, snum; + /* * Adjust flash start and offset to detected values */ @@ -233,14 +263,14 @@ int misc_init_r (void) /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); } @@ -252,8 +282,17 @@ int misc_init_r (void) (flash_info[0].start[0] - 1) + flash_info[0].size, &flash_info[0]); *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); + printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); + flash_info[0].size = 32 << 20; + for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); + flash_info[0].start[snum] < flash_sup_end; + snum++); + flash_info[0].sector_count = snum; } +#ifdef CONFIG_AUTO_UPDATE + do_auto_update(); +#endif return (0); } @@ -268,7 +307,7 @@ void pci_init_board(void) } #endif -#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) void init_ide_reset (void) { @@ -281,10 +320,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); } -#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ +#endif -#if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void doc_probe (ulong physadr); +#if defined(CONFIG_CMD_DOC) void doc_init (void) { doc_probe (CFG_DOC_BASE);