X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Flwmon5%2Fsdram.c;h=d4547e24cf1abed9f2b068a1b2ad86b79944201c;hb=93f798346033a1f6d22090b47abad4be88243b04;hp=b6863b6a79bb7d349dc5ba9bbfae7483334a7f39;hpb=8f085e324ad89423314b1a529a0dd5d85c8397ad;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index b6863b6..d4547e2 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -57,7 +57,6 @@
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
-#ifdef CONFIG_ADD_RAM_INFO
 static u32 is_ecc_enabled(void)
 {
 	u32 val;
@@ -87,7 +86,6 @@ void board_add_ram_info(int use_default)
 	val = DDR0_03_CASLAT_DECODE(val);
 	printf(", CL%d)", val);
 }
-#endif
 
 static int wait_for_dlllock(void)
 {
@@ -473,7 +471,7 @@ static void program_ecc(u32 start_address,
 		blank_string(strlen(str));
 	} else {
 		/* ECC bit set method for cached memory */
-#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 		/*
 		 * Some boards (like lwmon5) need to preserve the memory
 		 * content upon ECC generation (for the log-buffer).
@@ -486,6 +484,11 @@ static void program_ecc(u32 start_address,
 
 		current_address = start_address;
 		while (current_address < end_address) {
+			/*
+			 * TODO: Th following sequence doesn't work correctly.
+			 * Just invalidating and flushing the cache doesn't
+			 * seem to trigger the re-write of the memory.
+			 */
 			ppcDcbi(current_address);
 			ppcDcbf(current_address);
 			current_address += CFG_CACHELINE_SIZE;
@@ -514,19 +517,6 @@ static void program_ecc(u32 start_address,
 }
 #endif
 
-static __inline__ u32 get_mcsr(void)
-{
-	u32 val;
-
-	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-	return val;
-}
-
-static __inline__ void set_mcsr(u32 val)
-{
-	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
-}
-
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -534,8 +524,6 @@ static __inline__ void set_mcsr(u32 val)
  ************************************************************************/
 long int initdram (int board_type)
 {
-	u32 val;
-
 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
 	/* CL=3 */
 	mtsdram(DDR0_02, 0x00000000);
@@ -640,14 +628,6 @@ long int initdram (int board_type)
 	 * Perform data eye search if requested.
 	 */
 	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	val = get_mcsr();
-	set_mcsr(val);
 #endif
 
 #ifdef CONFIG_DDR_ECC
@@ -657,5 +637,12 @@ long int initdram (int board_type)
 	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
 #endif
 
+	/*
+	 * Clear possible errors resulting from data-eye-search.
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	set_mcsr(get_mcsr());
+
 	return (CFG_MBYTES_SDRAM << 20);
 }