X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Flogicpd%2Fomap3som%2Fomap3logic.c;h=559192e9001eb94e47b1c4284dc9a0a4a9e06e6f;hb=b8e09898919e23c5d7f1934be7bf9a3a6f0deb0e;hp=1da9e383c270a90ee0356ab54feffed4d224ea88;hpb=6e6cf015e7cdd7ca83a933320a81201972bd5e5e;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 1da9e38..559192e 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2011 * Logic Product Development @@ -8,25 +9,26 @@ * Derived from Beagle Board and 3430 SDP code by * Richard Woodruff * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include +#include #include -#include -#include #include #include +#include #include +#include #include #include #include #include #include #include +#include #include -#include +#include #include #include #include @@ -40,54 +42,23 @@ DECLARE_GLOBAL_DATA_PTR; -/* This is only needed until SPL gets OF support */ -#ifdef CONFIG_SPL_BUILD -static const struct ns16550_platdata omap3logic_serial = { - .base = OMAP34XX_UART1, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 -U_BOOT_DEVICE(omap3logic_uart) = { - "ns16550_serial", - &omap3logic_serial -}; -#endif +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 -/* - * two dimensional array of strucures containining board name and Linux - * machine IDs; row it selected based on CPU column is slected based - * on hsusb0_data5 pin having a pulldown resistor - */ -static struct board_id { - char *name; - int machine_id; - char *fdtfile; -} boards[2][2] = { - { - { - .name = "OMAP35xx SOM LV", - .machine_id = MACH_TYPE_OMAP3530_LV_SOM, - .fdtfile = "logicpd-som-lv-35xx-devkit.dtb", - }, - { - .name = "OMAP35xx Torpedo", - .machine_id = MACH_TYPE_OMAP3_TORPEDO, - .fdtfile = "logicpd-torpedo-35xx-devkit.dtb", - }, - }, - { - { - .name = "DM37xx SOM LV", - .fdtfile = "logicpd-som-lv-37xx-devkit.dtb", - }, - { - .name = "DM37xx Torpedo", - .fdtfile = "logicpd-torpedo-37xx-devkit.dtb", - }, - }, -}; +#define CONFIG_SMC911X_BASE 0x08000000 #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) @@ -108,68 +79,64 @@ int spl_start_uboot(void) void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mr = MICRON_V_MR_165; - /* 256MB DDR */ - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -} -#endif - -#ifdef CONFIG_USB_MUSB_OMAP2PLUS -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 16, - .ram_bits = 12, -}; - -static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_ULPI, -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_USB_MUSB_HOST) - .mode = MUSB_HOST, -#elif defined(CONFIG_USB_MUSB_GADGET) - .mode = MUSB_PERIPHERAL, -#else -#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET" -#endif - .config = &musb_config, - .power = 100, - .platform_ops = &omap2430_ops, - .board_data = &musb_board_data, -}; -#endif -#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD) -/* Call usb_stop() before starting the kernel */ -void show_boot_progress(int val) -{ - if (val == BOOTSTAGE_ID_RUN_OS) - usb_stop(); + if (get_cpu_family() == CPU_OMAP36XX) { + /* 200 MHz works for OMAP36/DM37 */ + /* 256MB DDR */ + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 165 MHz works for OMAP35 */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } -static struct omap_usbhs_board_data usbhs_bdata = { - .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, - .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED -}; +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) +void spl_board_prepare_for_linux(void) { - return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); -} + /* The Micron NAND starts locked which + * prohibits mounting the NAND as RW + * The following commands are what unlocks + * the NAND to become RW Falcon Mode does not + * have as many smarts as U-Boot, but Logic PD + * only makes NAND with 512MB so these hard coded + * values should work for all current models + */ -int ehci_hcd_stop(int index) -{ - return omap_ehci_hcd_stop(); + writeb(0x70, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x7a, GPMC_NAND_COMMAND_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_COMMAND_0); + + /* Begin address 0 */ + writeb(NAND_CMD_UNLOCK1, 0x6e00007c); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + + /* Ending address at the end of Flash */ + writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); + writeb(0xc0, GPMC_NAND_ADDRESS_0); + writeb(0xff, GPMC_NAND_ADDRESS_0); + writeb(0x03, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x79, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(-1, GPMC_NAND_DATA_0); } - -#endif /* CONFIG_USB_EHCI_HCD */ - +#endif /* * Routine: misc_init_r @@ -178,19 +145,32 @@ int ehci_hcd_stop(int index) int misc_init_r(void) { twl4030_power_init(); + twl4030_power_mmc_init(0); omap_die_id_display(); - -#ifdef CONFIG_USB_MUSB_OMAP2PLUS - musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); -#endif - return 0; } -/* - * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV - */ -#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ +#if defined(CONFIG_FLASH_CFI_DRIVER) +static const u32 gpmc_dm37_c2nor_config[] = { + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 +}; + +static const u32 gpmc_omap35_c2nor_config[] = { + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 +}; +#endif /* * Routine: board_init @@ -202,77 +182,29 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - +#if defined(CONFIG_FLASH_CFI_DRIVER) + if (get_cpu_family() == CPU_OMAP36XX) { + /* Enable CS2 for NOR Flash */ + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } else { + enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } +#endif return 0; } #ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - struct board_id *board; - unsigned int val; - - /* - * To identify between a SOM LV and Torpedo module, - * a pulldown resistor is on hsusb0_data5 for the SOM LV module. - * Drive the pin (and let it soak), then read it back. - * If the pin is still high its a Torpedo. If low its a SOM LV - */ - - /* Mux hsusb0_data5 as a GPIO */ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); - - if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { - - /* - * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV - * will drain the voltage. - */ - gpio_direction_output(BOARD_ID_GPIO, 0); - gpio_set_value(BOARD_ID_GPIO, 1); - - /* Let it soak for a bit */ - sdelay(0x100); - - /* - * Read state of BOARD_ID_GPIO as an input and if its set. - * If so the board is a Torpedo - */ - gpio_direction_input(BOARD_ID_GPIO); - val = gpio_get_value(BOARD_ID_GPIO); - gpio_free(BOARD_ID_GPIO); - - board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; - printf("Board: %s\n", board->name); - - /* Set the machine_id passed to Linux */ - if (board->machine_id) - gd->bd->bi_arch_number = board->machine_id; - /* If the user has not set fdtimage, set the default */ - if (!env_get("fdtimage")) - env_set("fdtimage", board->fdtfile); - } - - /* restore hsusb0_data5 pin as hsusb0_data5 */ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); - return 0; -} -#endif - -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) +static void unlock_nand(void) { - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif + int dev = nand_curr_device; + struct mtd_info *mtd; -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); + mtd = get_nand_dev_by_index(dev); + nand_unlock(mtd, 0, mtd->size, 0); } -#endif #ifdef CONFIG_SMC911X /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ @@ -284,14 +216,25 @@ static const u32 gpmc_lan92xx_config[] = { NET_LAN92XX_GPMC_CONFIG5, NET_LAN92XX_GPMC_CONFIG6, }; +#endif -int board_eth_init(bd_t *bis) +int board_late_init(void) { +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK + unlock_nand(); +#endif + +#ifdef CONFIG_SMC911X enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], CONFIG_SMC911X_BASE, GPMC_SIZE_16M); - - return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return 0; } #endif - +#if defined(CONFIG_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif