X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fkorat%2Fkorat.c;h=d5260dc232e4f9840ff606f1429fcd60df77bde3;hb=35e3717772c8c3534c18d8aac69e4b822777c23b;hp=0d90fb31dadb34bf763abeec235d38bdda0c41cf;hpb=9939ffd5fbf1f5aff4d8172531d4fc33797c62c8;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/korat/korat.c b/board/korat/korat.c index 0d90fb3..d5260dc 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006-2007 @@ -35,10 +35,11 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); @@ -46,11 +47,11 @@ ulong flash_get_size(ulong base, int banknum); void korat_buzzer(int const on) { if (on) { - out_8((u8 *) CFG_CPLD_BASE + 0x05, - in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80); } else { - out_8((u8 *) CFG_CPLD_BASE + 0x05, - in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80); } } #endif @@ -66,82 +67,82 @@ int board_early_init_f(void) extern void korat_branch_absolute(uint32_t addr); - for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) { + for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { udelay(1000); - if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) { + if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { /* This call does not return. */ korat_branch_absolute( - CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4); + CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); } } korat_buzzer(1); - while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) + while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) udelay(1000); korat_buzzer(0); #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - mtdcr(uic0er, 0x00000000); /* disable all */ - mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ - mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ - mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic0sr, 0xffffffff); /* clear all */ - - mtdcr(uic1sr, 0xffffffff); /* clear all */ - mtdcr(uic1er, 0x00000000); /* disable all */ - mtdcr(uic1cr, 0x00000000); /* all non-critical */ - mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic1sr, 0xffffffff); /* clear all */ - - mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtdcr(uic2er, 0x00000000); /* disable all */ - mtdcr(uic2cr, 0x00000000); /* all non-critical */ - mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ - mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ - mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ - mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ /* * Take sim card reader and CF controller out of reset. Also enable PHY * auto-detect until board-specific PHY resets are available. */ - out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. */ for (eth = 0; eth < 2; ++eth) { - if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) { + if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ - out_8((u8 *) CFG_CPLD_BASE + 0x03, - in_8((u8 *) CFG_CPLD_BASE + 0x03) | + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x06 << (4 * eth)); } else { /* SFP module present: configure PHY for fiber and enable output */ - gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1); - gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); + gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); } } /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ - gpio_write_bit(CFG_GPIO_PHY0_EN, 1); - gpio_write_bit(CFG_GPIO_PHY1_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ udelay(1000); - out_8((u8 *) CFG_CPLD_BASE + 0x03, - in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -157,8 +158,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); return 0; } @@ -176,8 +177,8 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) if (1 != banknum) return 0; - info->size = CFG_FLASH0_SIZE; - info->sector_count = CFG_FLASH0_SIZE / 0x20000; + info->size = CONFIG_SYS_FLASH0_SIZE; + info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000; info->flash_id = 0x01000000; info->portwidth = 2; info->chipwidth = 2; @@ -192,12 +193,12 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->manufacturer_id = 1; info->device_id = 0x007E; -#if CFG_FLASH0_SIZE == 0x01000000 +#if CONFIG_SYS_FLASH0_SIZE == 0x01000000 info->device_id2 = 0x2101; -#elif CFG_FLASH0_SIZE == 0x04000000 +#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 info->device_id2 = 0x2301; #else -#error Unable to set device_id2 for current CFG_FLASH0_SIZE +#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE #endif info->ext_addr = 0x0040; @@ -349,21 +350,22 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; - uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; char const *const act = getenv("usbact"); + char const *const usbcf = getenv("korat_usbcf"); /* * Re-do FLASH1 sizing and adjust flash start and offset. */ - gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size; + gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(flash1_size) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -375,36 +377,56 @@ int misc_init_r(void) * environment */ gd->bd->bi_flashoffset = - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR; + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21; + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ #if defined(CONFIG_KORAT_PERMANENT) - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, flash_info + 1); #else - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, flash_info); #endif /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, flash_info); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, flash_info); /* * USB suff... */ + /* + * Select the USB controller on the 440EPx ("ppc") or on the PCI bus + * ("pci") for the CompactFlash. + */ + if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) { + /* + * If environment variable "usbcf" is defined and set to "ppc", + * then connect the CompactFlash controller to the PowerPC USB + * port. + */ + printf("Attaching CompactFalsh controller to PPC USB\n"); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10); + } else { + if (usbcf != NULL && (strcmp(usbcf, "pci") != 0)) + printf("Warning: \"korat_usbcf\" is not set to a legal " + "value (\"ppc\" or \"pci\")\n"); + + printf("Attaching CompactFalsh controller to PCI USB\n"); + } if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -531,12 +553,12 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); set_serial_number(); set_mac_addresses(); - gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1); + gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1); return 0; } @@ -544,20 +566,20 @@ int misc_init_r(void) int checkboard(void) { char const *const s = getenv("serial#"); - u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); + u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0); printf("Board: Korat, Rev. %X", rev); if (s) printf(", serial# %s", s); printf(".\n Ethernet PHY 0: "); - if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL)) + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL)) printf("fiber"); else printf("copper"); printf(", PHY 1: "); - if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL)) + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL)) printf("fiber"); else printf("copper"); @@ -573,134 +595,24 @@ int checkboard(void) /* * Assign interrupts to PCI devices. */ -void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); } #endif /* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); - - /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); - -#if defined(CONFIG_PCI_PNP) - hose->fixup_irq = korat_pci_fixup_irq; -#endif - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* * pci_target_init * * The bootstrap configuration provides default settings for the pci * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF - * ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, - CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, - CFG_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, - CFG_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + /* First do 440EP(x) common setup */ + __pci_target_init(hose); /* * Set up Configuration registers for on-board NEC uPD720101 USB @@ -708,56 +620,7 @@ void pci_target_init(struct pci_controller *hose) */ pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - */ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif - -/* - * is_pci_host - * - * This routine is called to determine if a pci scan should be - * performed. With various hardware environments (especially cPCI and - * PPMC) it's insufficient to depend on the state of the arbiter enable - * bit in the strap register, or generic host/adapter assumptions. - * - * Rather than hard-code a bad assumption in the general 440 code, the - * 440 pci code requires the board to decide at runtime. - * - * Return 0 for adapter mode, non-zero for host (monarch) mode. - */ -#if defined(CONFIG_PCI) -int is_pci_host(struct pci_controller *hose) -{ - /* Korat is always configured as host. */ - return (1); -} -#endif /* defined(CONFIG_PCI) */ - -#if defined(CONFIG_POST) -/* - * Returns 1 if keys pressed to start the power-on long-running tests - * Called from board_init_f(). - */ -int post_hotkeys_pressed(void) -{ - return 0; /* No hotkeys supported */ -} -#endif /* CONFIG_POST */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) @@ -771,7 +634,7 @@ void ft_board_setup(void *blob, bd_t *bd) val[0] = 1; /* chip select number */ val[1] = 0; /* always 0 */ val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", val, sizeof(val), 1); if (rc)