X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fkeymile%2Fkmcent2%2Ftlb.c;h=41b24e39433d55bd14a32e6afce32b989cc6796b;hb=65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8;hp=dbd3b9b064cc46085807b04eea922104ef322e93;hpb=2ae80437fbe0181184ae4b188b89629b902702c6;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
index dbd3b9b..41b24e3 100644
--- a/board/keymile/kmcent2/tlb.c
+++ b/board/keymile/kmcent2/tlb.c
@@ -11,20 +11,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+	SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -35,56 +35,56 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
 		      MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
 		      0, 2, BOOKE_PAGESZ_128M, 1),
 
 	/* *I*G* - PCI1 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI1 I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+	SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 8, BOOKE_PAGESZ_16M, 1),
 
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 9, BOOKE_PAGESZ_4M, 1),
 
 	/* *I*G - NAND */
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 	/* QRIO */
-	SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 11, BOOKE_PAGESZ_64K, 1),
 	/* MRAM */
-	SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 12, BOOKE_PAGESZ_128M, 1),
 	/* BFTIC */
@@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * in cpu_init_f, so do not use them here!!.
 	 */
 	/* PAXE */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
+	SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
 		      MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		      0, 16, BOOKE_PAGESZ_128M, 1)
 };