X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fisee%2Figep00x0%2Figep00x0.c;h=65cc7dfdecefb3586ce6fcdab4533680636c9c84;hb=2d8d190c8394b43c0989cdb04a50cb48d4e1f8da;hp=57b89e0ba64e882177b5405be7ce90cbefd2d69c;hpb=c1924d85af4a07dc70aef1ef95c48b54a136733f;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 57b89e0..65cc7df 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -17,26 +18,22 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include "igep00x0.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NET) -/* GPMC definitions for LAN9221 chips */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, -}; -#endif - static const struct ns16550_platdata igep_serial = { - OMAP34XX_UART3, - 2, - V_NS16550_CLK + .base = OMAP34XX_UART3, + .reg_shift = 2, + .clock = V_NS16550_CLK, + .fcr = UART_FCR_DEFVAL, }; U_BOOT_DEVICE(igep_uart) = { @@ -50,12 +47,30 @@ U_BOOT_DEVICE(igep_uart) = { */ int board_init(void) { - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); -#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) - status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); #endif return 0; @@ -63,44 +78,84 @@ int board_init(void) #ifdef CONFIG_SPL_BUILD /* - * Routine: omap_rev_string - * Description: For SPL builds output board rev - */ -void omap_rev_string(void) -{ -} - -/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { - timings->mr = MICRON_V_MR_165; -#ifdef CONFIG_BOOT_NAND - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -#else - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + int mfr, id, err = identify_nand_chip(&mfr, &id); - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->mr = MICRON_V_MR_165; + if (!err) { + switch (mfr) { + case NAND_MFR_HYNIX: + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + break; + case NAND_MFR_MICRON: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + break; + default: + /* Should not happen... */ + break; + } timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; } -#endif +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; } #endif +#endif + +int onenand_board_init(struct mtd_info *mtd) +{ + if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { + struct onenand_chip *this = mtd->priv; + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + return 0; + } + return 1; +} #if defined(CONFIG_CMD_NET) +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -109,9 +164,17 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + }; - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -121,15 +184,16 @@ static void setup_net_chip(void) writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } + reset_net_chip(64); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; +#endif } #else static inline void setup_net_chip(void) {} @@ -149,6 +213,21 @@ void board_mmc_power_init(void) } #endif +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + static struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, + { "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, }, + }; + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + return 0; +} +#endif + void set_fdt(void) { switch (gd->bd->bi_arch_number) { @@ -178,6 +257,23 @@ int misc_init_r(void) return 0; } +void board_mtdparts_default(const char **mtdids, const char **mtdparts) +{ + struct mtd_info *mtd = get_mtd_device(NULL, 0); + if (mtd) { + static char ids[24]; + static char parts[48]; + const char *linux_name = "omap2-nand"; + if (strncmp(mtd->name, "onenand0", 8) == 0) + linux_name = "omap2-onenand"; + snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); + snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", + linux_name, 4 * mtd->erasesize >> 10); + *mtdids = ids; + *mtdparts = parts; + } +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the @@ -196,14 +292,3 @@ void set_muxconf_regs(void) MUX_IGEP0030(); #endif } - -#if defined(CONFIG_CMD_NET) -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} -#endif