X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fids8247%2Fids8247.c;h=1b2d0e09a9511820afcfab82fb58fd0ca2d4aa79;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=b05424d32b29a2cf3120445dc2d0da2f6bd398ad;hpb=5c568d6a7f950b9e7e32a63a5893f979b8789b4d;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index b05424d..1b2d0e0 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -2,23 +2,7 @@ * (C) Copyright 2005 * Heiko Schocher, DENX Software Engineering, * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -51,7 +35,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ -#if defined(CONFIG_SOFT_I2C) +#if defined(CONFIG_SYS_I2C_SOFT) /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */ #else /* normal I/O port pins */ @@ -254,7 +238,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -265,7 +249,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -276,25 +260,24 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -long int initdram (int board_type) +phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - long psize, lsize; + long psize; psize = 16 * 1024 * 1024; - lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR2, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ + psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, + (uchar *) CONFIG_SYS_SDRAM_BASE); +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -304,55 +287,104 @@ long int initdram (int board_type) int misc_init_r (void) { gd->bd->bi_flashstart = 0xff800000; + return 0; } #if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe (ulong physadr); +#include +#include +#include -void -nand_init (void) -{ - ulong totlen = 0; +static u8 hwctl; - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); +static void ids_nand_hwctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) { + hwctl |= 0x1; + writeb(0x00, (this->IO_ADDR_W + 0x0a)); + } else { + hwctl &= ~0x1; + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if ( ctrl & NAND_ALE ) { + hwctl |= 0x2; + writeb(0x00, (this->IO_ADDR_W + 0x09)); + } else { + hwctl &= ~0x2; + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if ( (ctrl & NAND_NCE) != NAND_NCE) + writeb(0x00, (this->IO_ADDR_W + 0x0c)); + else + writeb(0x00, (this->IO_ADDR_W + 0x08)); + } + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); - printf ("%4lu MB\n", totlen >>20); } -#endif /* CFG_CMD_NAND */ +static u_char ids_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + return readb(this->IO_ADDR_R); +} -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -/* - * update "memory" property in the blob - */ -void ft_blob_update(void *blob, bd_t *bd) +static void ids_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { - int ret, nodeoffset = 0; - ulong memory_data[2] = {0}; - - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); - - nodeoffset = fdt_find_node_by_path (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) - printf("ft_blob_update): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); + struct nand_chip *nand = mtd->priv; + int i; + + for (i = 0; i < len; i++) { + if (hwctl & 0x1) + writeb(buf[i], (nand->IO_ADDR_W + 0x02)); + else if (hwctl & 0x2) + writeb(buf[i], (nand->IO_ADDR_W + 0x01)); + else + writeb(buf[i], nand->IO_ADDR_W); } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); +} + +static void ids_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + int i; + + for (i = 0; i < len; i++) { + buf[i] = readb(this->IO_ADDR_R); } } +static int ids_nand_dev_ready(struct mtd_info *mtd) +{ + /* constant delay (see also tR in the datasheet) */ + udelay(12); + return 1; +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + + /* Reference hardware control function */ + nand->cmd_ctrl = ids_nand_hwctrl; + nand->read_byte = ids_nand_read_byte; + nand->write_buf = ids_nand_write_buf; + nand->read_buf = ids_nand_read_buf; + nand->dev_ready = ids_nand_dev_ready; + nand->chip_delay = 12; + + return 0; +} + +#endif /* CONFIG_CMD_NAND */ + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */