X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fgdsys%2F405ex%2Fio64.c;h=9ef965bbfa35a96751266560e42da6a6cfad63ba;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=fa8961a35177a78cd9de65b4596166a5554862bd;hpb=8b485ba12b0defa0c4ed3559789250238f8331a8;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index fa8961a..9ef965bb 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -15,7 +15,7 @@
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/ppc4xx-gpio.h>
 #include <flash.h>
 
@@ -26,7 +26,6 @@
 
 #include <miiphy.h>
 #include <i2c.h>
-#include <dtt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,6 +50,8 @@ enum {
 	HWVER_110 = 1,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 static inline void blank_string(int size)
 {
 	int i;
@@ -68,8 +69,13 @@ static inline void blank_string(int size)
  */
 int misc_init_r(void)
 {
-	/* startup fans */
-	dtt_init();
+	/*
+	 * Note: DTT has been removed. Please use UCLASS_THERMAL.
+	 *
+	 * startup fans
+	 *
+	 * dtt_init();
+	 */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
@@ -84,10 +90,9 @@ int misc_init_r(void)
 
 static void print_fpga_info(unsigned dev)
 {
-	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-	u16 versions = in_le16(&fpga->versions);
-	u16 fpga_version = in_le16(&fpga->fpga_version);
-	u16 fpga_features = in_le16(&fpga->fpga_features);
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
 	int fpga_state = get_fpga_state(dev);
 
 	unsigned unit_type;
@@ -95,6 +100,10 @@ static void print_fpga_info(unsigned dev)
 	unsigned feature_channels;
 	unsigned feature_expansion;
 
+	FPGA_GET_REG(dev, versions, &versions);
+	FPGA_GET_REG(dev, fpga_version, &fpga_version);
+	FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
 	printf("FPGA%d: ", dev);
 	if (fpga_state & FPGA_STATE_PLATFORM)
 		printf("(legacy) ");
@@ -226,8 +235,6 @@ int last_stage_init(void)
 {
 	unsigned int k;
 	unsigned int fpga;
-	struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-	struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
 	int failed = 0;
 	char str_phys[] = "Setup PHYs -";
 	char str_serdes[] = "Start SERDES blocks";
@@ -243,8 +250,17 @@ int last_stage_init(void)
 	/* setup Gbit PHYs */
 	puts("TRANS: ");
 	puts(str_phys);
-	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
-		bb_miiphy_read, bb_miiphy_write);
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
 
 	for (k = 0; k < 32; ++k) {
 		configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
@@ -252,8 +268,16 @@ int last_stage_init(void)
 		putc(slash[k % 8]);
 	}
 
-	miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
-		bb_miiphy_read, bb_miiphy_write);
+	mdiodev = mdio_alloc();
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
 
 	for (k = 0; k < 32; ++k) {
 		configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
@@ -265,17 +289,16 @@ int last_stage_init(void)
 	/* take fpga serdes blocks out of reset */
 	puts(str_serdes);
 	udelay(500000);
-	out_le16(&fpga0->quad_serdes_reset, 0);
-	out_le16(&fpga1->quad_serdes_reset, 0);
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
+	FPGA_SET_REG(1, quad_serdes_reset, 0);
 	blank_string(strlen(str_serdes));
 
 	/* take channels out of reset */
 	puts(str_channels);
 	udelay(500000);
 	for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
 		for (k = 0; k < 32; ++k)
-			out_le16(ch0_config_int + 4 * k, 0);
+			FPGA_SET_REG(fpga, ch[k].config_int, 0);
 	}
 	blank_string(strlen(str_channels));
 
@@ -283,16 +306,16 @@ int last_stage_init(void)
 	puts(str_locks);
 	udelay(500000);
 	for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
 		for (k = 0; k < 32; ++k) {
-			u16 status = in_le16(ch0_status_int + 4*k);
+			u16 status;
+			FPGA_GET_REG(fpga, ch[k].status_int, &status);
 			if (!(status & (1 << 4))) {
 				failed = 1;
 				printf("fpga %d channel %d: no serdes lock\n",
 					fpga, k);
 			}
 			/* reset events */
-			out_le16(ch0_status_int + 4*k, status);
+			FPGA_SET_REG(fpga, ch[k].status_int, 0);
 		}
 	}
 	blank_string(strlen(str_locks));
@@ -300,14 +323,14 @@ int last_stage_init(void)
 	/* verify hicb_status */
 	puts(str_hicb);
 	for (fpga = 0; fpga < 2; ++fpga) {
-		u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
 		for (k = 0; k < 32; ++k) {
-			u16 status = in_le16(ch0_hicb_status_int + 4*k);
+			u16 status;
+			FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
 			if (status)
 				printf("fpga %d hicb %d: hicb status %04x\n",
 					fpga, k, status);
 			/* reset events */
-			out_le16(ch0_hicb_status_int + 4*k, status);
+			FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
 		}
 	}
 	blank_string(strlen(str_hicb));