X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fgdsys%2F405ex%2Fio64.c;h=9ef965bbfa35a96751266560e42da6a6cfad63ba;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=2f8e306261815acd00e51137c31d2034acf34b4b;hpb=e20cc2ca15b5b0644f51b6e58d530d70acd2bc00;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 2f8e306..9ef965bb 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -15,7 +15,7 @@
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/ppc4xx-gpio.h>
 #include <flash.h>
 
@@ -26,7 +26,6 @@
 
 #include <miiphy.h>
 #include <i2c.h>
-#include <dtt.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,8 +69,13 @@ static inline void blank_string(int size)
  */
 int misc_init_r(void)
 {
-	/* startup fans */
-	dtt_init();
+	/*
+	 * Note: DTT has been removed. Please use UCLASS_THERMAL.
+	 *
+	 * startup fans
+	 *
+	 * dtt_init();
+	 */
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
@@ -246,8 +250,17 @@ int last_stage_init(void)
 	/* setup Gbit PHYs */
 	puts("TRANS: ");
 	puts(str_phys);
-	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
-		bb_miiphy_read, bb_miiphy_write);
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
 
 	for (k = 0; k < 32; ++k) {
 		configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
@@ -255,8 +268,16 @@ int last_stage_init(void)
 		putc(slash[k % 8]);
 	}
 
-	miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
-		bb_miiphy_read, bb_miiphy_write);
+	mdiodev = mdio_alloc();
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
 
 	for (k = 0; k < 32; ++k) {
 		configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
@@ -287,7 +308,7 @@ int last_stage_init(void)
 	for (fpga = 0; fpga < 2; ++fpga) {
 		for (k = 0; k < 32; ++k) {
 			u16 status;
-			FPGA_GET_REG(k, ch[k].status_int, &status);
+			FPGA_GET_REG(fpga, ch[k].status_int, &status);
 			if (!(status & (1 << 4))) {
 				failed = 1;
 				printf("fpga %d channel %d: no serdes lock\n",
@@ -304,7 +325,7 @@ int last_stage_init(void)
 	for (fpga = 0; fpga < 2; ++fpga) {
 		for (k = 0; k < 32; ++k) {
 			u16 status;
-			FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
+			FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
 			if (status)
 				printf("fpga %d hicb %d: hicb status %04x\n",
 					fpga, k, status);