X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fgdsys%2F405ex%2Fio64.c;h=9ef965bbfa35a96751266560e42da6a6cfad63ba;hb=853eaa4f301c15584f3664f1be000921810d7825;hp=a997571f0ba2de9556689b7188ac0cc9731b3ee1;hpb=255ef4d9091fe896ff152629a8cb290ee92c9fde;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index a997571..9ef965bb 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -5,23 +5,7 @@ * based on kilauea.c * by Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -31,7 +15,7 @@ #include #include #include -#include +#include #include #include @@ -42,7 +26,6 @@ #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -67,6 +50,8 @@ enum { HWVER_110 = 1, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + static inline void blank_string(int size) { int i; @@ -84,8 +69,13 @@ static inline void blank_string(int size) */ int misc_init_r(void) { - /* startup fans */ - dtt_init(); + /* + * Note: DTT has been removed. Please use UCLASS_THERMAL. + * + * startup fans + * + * dtt_init(); + */ #ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ @@ -100,10 +90,9 @@ int misc_init_r(void) static void print_fpga_info(unsigned dev) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; int fpga_state = get_fpga_state(dev); unsigned unit_type; @@ -111,6 +100,10 @@ static void print_fpga_info(unsigned dev) unsigned feature_channels; unsigned feature_expansion; + FPGA_GET_REG(dev, versions, &versions); + FPGA_GET_REG(dev, fpga_version, &fpga_version); + FPGA_GET_REG(dev, fpga_features, &fpga_features); + printf("FPGA%d: ", dev); if (fpga_state & FPGA_STATE_PLATFORM) printf("(legacy) "); @@ -242,13 +235,12 @@ int last_stage_init(void) { unsigned int k; unsigned int fpga; - ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); - ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; char str_channels[] = "Start FPGA channels"; char str_locks[] = "Verify SERDES locks"; + char str_hicb[] = "Verify HICB status"; char str_status[] = "Verify PHY status -"; char slash[] = "\\|/-\\|/-"; @@ -258,8 +250,17 @@ int last_stage_init(void) /* setup Gbit PHYs */ puts("TRANS: "); puts(str_phys); - miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); @@ -267,8 +268,16 @@ int last_stage_init(void) putc(slash[k % 8]); } - miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, - bb_miiphy_read, bb_miiphy_write); + mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); @@ -280,17 +289,16 @@ int last_stage_init(void) /* take fpga serdes blocks out of reset */ puts(str_serdes); udelay(500000); - out_le16(&fpga0->quad_serdes_reset, 0); - out_le16(&fpga1->quad_serdes_reset, 0); + FPGA_SET_REG(0, quad_serdes_reset, 0); + FPGA_SET_REG(1, quad_serdes_reset, 0); blank_string(strlen(str_serdes)); /* take channels out of reset */ puts(str_channels); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; for (k = 0; k < 32; ++k) - out_le16(ch0_config_int + 4 * k, 0); + FPGA_SET_REG(fpga, ch[k].config_int, 0); } blank_string(strlen(str_channels)); @@ -298,20 +306,35 @@ int last_stage_init(void) puts(str_locks); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; for (k = 0; k < 32; ++k) { - u16 status = in_le16(ch0_status_int + 4*k); + u16 status; + FPGA_GET_REG(fpga, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); } /* reset events */ - out_le16(ch0_status_int + 4*k, status); + FPGA_SET_REG(fpga, ch[k].status_int, 0); } } blank_string(strlen(str_locks)); + /* verify hicb_status */ + puts(str_hicb); + for (fpga = 0; fpga < 2; ++fpga) { + for (k = 0; k < 32; ++k) { + u16 status; + FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status); + if (status) + printf("fpga %d hicb %d: hicb status %04x\n", + fpga, k, status); + /* reset events */ + FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); + } + } + blank_string(strlen(str_hicb)); + /* verify phy status */ puts(str_status); for (k = 0; k < 32; ++k) { @@ -343,7 +366,7 @@ void gd405ex_init(void) if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) - gd->fpga_state[k] |= FPGA_STATE_PLATFORM; + gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; } else { pca9698_direction_output(0x22, 39, 1); }