X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fgdsys%2F405ep%2Fio.c;h=1484469bb04fc78feed609694c39296f2b5ca5bd;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=80877b61ffa525d0d6c4d068d26f85bbb6618735;hpb=1032d97496f6d534bf0030a5779ff1cb38cc9ebf;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 80877b6..1484469 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -29,7 +13,12 @@
 
 #include <miiphy.h>
 
-#include "../common/fpga.h"
+#include "405ep.h"
+#include <gdsys_fpga.h>
+
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
 
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22
@@ -37,13 +26,6 @@
 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
 
 enum {
-	REG_VERSIONS = 0x0002,
-	REG_FPGA_FEATURES = 0x0004,
-	REG_FPGA_VERSION = 0x0006,
-	REG_QUAD_SERDES_RESET = 0x0012,
-};
-
-enum {
 	UNITTYPE_CCD_SWITCH = 1,
 };
 
@@ -54,6 +36,21 @@ enum {
 	HWVER_122 = 3,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
+int misc_init_r(void)
+{
+	/*
+	 * Note: DTT has been removed. Please use UCLASS_THERMAL.
+	 *
+	 * startup fans
+	 *
+	 * dtt_init();
+	 */
+
+	return 0;
+}
+
 int configure_gbit_phy(unsigned char addr)
 {
 	unsigned short value;
@@ -95,28 +92,39 @@ err_out:
 int checkboard(void)
 {
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+
+	puts("Board: CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	u16 versions;
+	u16 fpga_version;
+	u16 fpga_features;
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_channels;
 	unsigned feature_expansion;
 
+	FPGA_GET_REG(0, versions, &versions);
+	FPGA_GET_REG(0, fpga_version, &fpga_version);
+	FPGA_GET_REG(0, fpga_features, &fpga_features);
+
 	unit_type = (versions & 0xf000) >> 12;
 	hardware_version = versions & 0x000f;
 	feature_channels = fpga_features & 0x007f;
 	feature_expansion = fpga_features & (1<<15);
 
-	printf("Board: ");
-
-	printf("CATCenter Io");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-	puts("\n       ");
+	puts("FPGA:  ");
 
 	switch (unit_type) {
 	case UNITTYPE_CCD_SWITCH:
@@ -157,8 +165,6 @@ int checkboard(void)
 	printf(" %d channel(s)", feature_channels);
 
 	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
-	return 0;
 }
 
 /*
@@ -168,14 +174,54 @@ int last_stage_init(void)
 {
 	unsigned int k;
 
-	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
-		bb_miiphy_read, bb_miiphy_write);
+	print_fpga_info();
+
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
 
 	for (k = 0; k < 32; ++k)
 		configure_gbit_phy(k);
 
 	/* take fpga serdes blocks out of reset */
-	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+	FPGA_SET_REG(0, quad_serdes_reset, 0);
 
 	return 0;
 }
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}