X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Fgdsys%2F405ep%2F405ep.c;h=35fa06a2ee97825f0aea09b1b724477357376858;hb=d4db3b86a5e090e21db710bedbbe3e50d4c56428;hp=d3bd2330943b573c4d1264e10f3aa8b118b9a4b3;hpb=7ad1a5f69d6da7335aa884f76d76df6f5130cd4b;p=platform%2Fkernel%2Fu-boot.git

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..35fa06a 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2010
  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -26,18 +10,34 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
 
-#include "../common/fpga.h"
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+#include "405ep.h"
+#include <gdsys_fpga.h>
 
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->arch.fpga_state[dev];
+}
+
 int board_early_init_f(void)
 {
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
+
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
 	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
@@ -51,42 +51,63 @@ int board_early_init_f(void)
 	 * -> ca. 15 us
 	 */
 	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
+	return 0;
+}
 
-	/*
-	 * setup io-latches for reset
-	 */
-	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+int board_early_init_r(void)
+{
+	unsigned k;
+	unsigned ctr;
 
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->arch.fpga_state[k] = 0;
 
 	/*
-	 * wait for fpga-done
-	 * fail ungraceful if fpga is not configuring properly
+	 * reset FPGA
 	 */
-	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
-		;
+	gd405ep_init();
+
+	gd405ep_set_fpga_reset(1);
+
+	gd405ep_setup_hw();
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!gd405ep_get_fpga_done(k)) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
 
-	/*
-	 * setup io-latches for boot (stop reset)
-	 */
 	udelay(10);
-	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 
-	/*
-	 * wait for fpga out of reset
-	 * fail ungraceful if fpga is not working properly
-	 */
-	while (1) {
-		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
-		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
-			REFLECTION_TESTPATTERN_INV)
-			break;
+	gd405ep_set_fpga_reset(0);
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 */
+		ctr = 0;
+		while (1) {
+			u16 val;
+
+			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
+
+			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+			if (val == REFLECTION_TESTPATTERN_INV)
+				break;
+
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->arch.fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
 	}
 
 	return 0;