X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=board%2Ffreescale%2Ft208xqds%2Feth_t208xqds.c;h=aaa3490aaa2ab63ffce3dcd3f84d0e094d979ed6;hb=5a1a8a63be8f7262a300eddafb18020926b12fb6;hp=d7a804d22ad937bbb5839911a79adb58ec36c9b5;hpb=08798026f24bd7c706e70372f8c323f0702c9a15;p=platform%2Fkernel%2Fu-boot.git diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index d7a804d..aaa3490 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -1,13 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * * Shengzhou Liu - * - * SPDX-License-Identifier: GPL-2.0+ */ #include #include +#include +#include +#include #include #include #include @@ -21,23 +24,25 @@ #include #include #include -#include +#include #include +#include #include "../common/qixis.h" #include "../common/fman.h" #include "t208xqds_qixis.h" +#include #define EMI_NONE 0xFFFFFFFF #define EMI1_RGMII1 0 #define EMI1_RGMII2 1 #define EMI1_SLOT1 2 -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) #define EMI1_SLOT2 6 #define EMI1_SLOT3 3 #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 #define EMI2 7 -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) #define EMI1_SLOT2 3 #define EMI1_SLOT3 4 #define EMI1_SLOT5 5 @@ -46,10 +51,19 @@ #define EMI2 8 #endif +#define PCCR1_SGMIIA_KX_MASK 0x00008000 +#define PCCR1_SGMIIB_KX_MASK 0x00004000 +#define PCCR1_SGMIIC_KX_MASK 0x00002000 +#define PCCR1_SGMIID_KX_MASK 0x00001000 +#define PCCR1_SGMIIE_KX_MASK 0x00000800 +#define PCCR1_SGMIIF_KX_MASK 0x00000400 +#define PCCR1_SGMIIG_KX_MASK 0x00000200 +#define PCCR1_SGMIIH_KX_MASK 0x00000100 + static int mdio_mux[NUM_FM_PORTS]; static const char * const mdio_names[] = { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) "T2080QDS_MDIO_RGMII1", "T2080QDS_MDIO_RGMII2", "T2080QDS_MDIO_SLOT1", @@ -58,7 +72,7 @@ static const char * const mdio_names[] = { "T2080QDS_MDIO_SLOT5", "T2080QDS_MDIO_SLOT2", "T2080QDS_MDIO_10GC", -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) "T2081QDS_MDIO_RGMII1", "T2081QDS_MDIO_RGMII2", "T2081QDS_MDIO_SLOT1", @@ -72,9 +86,9 @@ static const char * const mdio_names[] = { }; /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; #endif @@ -166,7 +180,7 @@ static int t208xqds_mdio_init(char *realbusname, u8 muxval) bus->read = t208xqds_mdio_read; bus->write = t208xqds_mdio_write; bus->reset = t208xqds_mdio_reset; - sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); + strcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); @@ -187,8 +201,19 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, { int phy; char alias[20]; + char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"}; + char buf[32] = "serdes-1,"; struct fixed_link f_link; + int media_type = 0; + const char *phyconn; + int off; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_TARGET_T2080QDS + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); +#endif u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -197,11 +222,56 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { phy = fm_info_get_phy_address(port); switch (port) { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case FM1_DTSEC1: + if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx1"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIH_KX_MASK); + break; + } case FM1_DTSEC2: + if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx2"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIG_KX_MASK); + break; + } case FM1_DTSEC9: + if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx9"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIE_KX_MASK); + break; + } case FM1_DTSEC10: + if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx10"); + fdt_status_okay_by_alias(fdt, + "1gkx_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIF_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT2) { sprintf(alias, "phy_sgmii_s2_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -213,7 +283,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } break; case FM1_DTSEC5: + if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx5"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); + sprintf(buf, "%s%s%s", buf, "lane-g,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIIC_KX_MASK); + break; + } case FM1_DTSEC6: + if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) { + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_1gkx6"); + fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); + sprintf(buf, "%s%s%s", buf, "lane-h,", + (char *)lane_mode[0]); + out_be32(&srds_regs->srdspccr1, srds1_pccr1 | + PCCR1_SGMIID_KX_MASK); + break; + } if (mdio_mux[port] == EMI1_SLOT1) { sprintf(alias, "phy_sgmii_s1_%x", phy); fdt_set_phy_handle(fdt, compat, addr, alias); @@ -224,7 +316,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_status_okay_by_alias(fdt, "emi1_slot2"); } break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC5: @@ -257,6 +349,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, default: break; } + if (media_type) { + /* set property for 1000BASE-KX in dtb */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, "lane-instance", buf); + } } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { @@ -265,15 +363,86 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, case 0x6c: case 0x6d: case 0x71: - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); + /* + * if the 10G is XFI, check hwconfig to see what is the + * media type, there are two types, fiber or copper, + * fix the dtb accordingly. + */ + switch (port) { + case FM1_10GEC1: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { + /* it's MAC9 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi9"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); + sprintf(buf, "%s%s%s", buf, "lane-a,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC2: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { + /* it's MAC10 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi10"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); + sprintf(buf, "%s%s%s", buf, "lane-b,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC3: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) { + /* it's MAC1 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi1"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); + sprintf(buf, "%s%s%s", buf, "lane-c,", + (char *)lane_mode[1]); + } + break; + case FM1_10GEC4: + if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) { + /* it's MAC2 */ + media_type = 1; + fdt_set_phy_handle(fdt, compat, addr, + "phy_xfi2"); + fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); + sprintf(buf, "%s%s%s", buf, "lane-d,", + (char *)lane_mode[1]); + } + break; + default: + return; + } + + if (!media_type) { + phyconn = fdt_getprop(fdt, offset, + "phy-connection-type", + NULL); + if (is_backplane_mode(phyconn)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", + port); + } else { + /* fixed-link for XFI fiber cable */ + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", + &f_link, sizeof(f_link)); + } + } else { + /* set property for copper cable */ + off = fdt_node_offset_by_compat_reg(fdt, + "fsl,fman-memac-mdio", addr + 0x1000); + fdt_setprop_string(fdt, off, + "lane-instance", buf); + } break; default: break; @@ -299,7 +468,7 @@ static void initialize_lane_to_slot(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; switch (srds_s1) { -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case 0x51: case 0x5f: case 0x65: @@ -326,7 +495,7 @@ static void initialize_lane_to_slot(void) lane_to_slot[6] = 3; lane_to_slot[7] = 3; break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case 0x6b: lane_to_slot[4] = 1; lane_to_slot[5] = 3; @@ -356,7 +525,7 @@ static void initialize_lane_to_slot(void) } } -int board_eth_init(bd_t *bis) +int board_eth_init(struct bd_info *bis) { #if defined(CONFIG_FMAN_ENET) int i, idx, lane, slot, interface; @@ -397,11 +566,11 @@ int board_eth_init(bd_t *bis) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); #endif t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); -#if defined(CONFIG_T2081QDS) +#if defined(CONFIG_TARGET_T2081QDS) t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); #endif @@ -416,6 +585,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); switch (srds_s1) { + case 0x1b: case 0x1c: case 0x95: case 0xa2: @@ -429,8 +599,11 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; + case 0x50: case 0x51: + case 0x5e: case 0x5f: + case 0x64: case 0x65: /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); @@ -439,8 +612,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); break; case 0x66: + case 0x67: /* - * XFI does not need a PHY to work, but to avoid U-boot use + * XFI does not need a PHY to work, but to avoid U-Boot use * default PHY address which is zero to a MAC when it found * a MAC has no PHY address, we give a PHY address to XFI * MAC, and should not use a real XAUI PHY address, since @@ -453,6 +627,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_10GEC3, 6); fm_info_set_phy_address(FM1_10GEC4, 7); break; + case 0x6a: case 0x6b: fm_info_set_phy_address(FM1_10GEC1, 4); fm_info_set_phy_address(FM1_10GEC2, 5); @@ -470,6 +645,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; + case 0x70: case 0x71: /* SGMII in Slot3 */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); @@ -501,7 +677,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); break; -#if defined(CONFIG_T2080QDS) +#if defined(CONFIG_TARGET_T2080QDS) case 0xd9: case 0xd3: case 0xcb: @@ -513,7 +689,7 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); break; -#elif defined(CONFIG_T2081QDS) +#elif defined(CONFIG_TARGET_T2081QDS) case 0xca: case 0xcb: /* SGMII in Slot3 */ @@ -569,7 +745,7 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval( mdio_mux[i])); break; -#if defined(CONFIG_T2081QDS) +#if defined(CONFIG_TARGET_T2081QDS) case 5: mdio_mux[i] = EMI1_SLOT5; fm_info_set_mdio(i, mii_dev_for_muxval( @@ -589,6 +765,9 @@ int board_eth_init(bd_t *bis) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: if (i == FM1_DTSEC3) mdio_mux[i] = EMI1_RGMII1; else if (i == FM1_DTSEC4 || FM1_DTSEC10) @@ -625,6 +804,7 @@ int board_eth_init(bd_t *bis) fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { /* As XFI is in cage intead of a slot, so